vga.map.smsg

来自「用来实现VGA发生时序」· SMSG 代码 · 共 3 行

Info (10281): Verilog HDL Declaration information at vga_tgen.v(41): object "vgate" differs only in case from object "Vgate" in the same scope
Warning (10236): Verilog HDL Implicit Net warning at vga_tgen.v(81): created implicit net for "eof"