代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/439761/7701942
vhd top_level_tb.vhd
-- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY TOP_LEVEL_TB IS
END TOP_LEVEL_TB;
ARCHITECTURE BEHAVE OF TOP_LEVEL_TB IS
-- *********
www.eeworm.com/read/197089/8031679
vhd test_bench.vhd
-- Test Bench for kcpsm2_int_test.vhd
--
-- Ken Chapman - Xilinx Ltd - February 2002
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testb
www.eeworm.com/read/341882/12056507
v text_bench.v
module testbench;
parameter width=8;
wire [width-1:0] address_out;
wire [width-1:0] data_cm_bus;
wire S;
wire R;
wire D;
reg clk;
reg reset;
mainboard
www.eeworm.com/read/219674/14870826
vhd data_lock_test.vhd
-- VHDL Test Bench Created from source file data_lock.vhd -- 21:22:03 12/13/2006
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector fo
www.eeworm.com/read/219674/14870943
vhd counter10_test.vhd
-- VHDL Test Bench Created from source file counter10.vhd -- 09:47:06 12/15/2006
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector fo
www.eeworm.com/read/17937/767654
tf mul3_1_casz_tb.tf
module testbench();
// Inputs
reg [2:0] sel;
reg [3:0] a;
reg [3:0] b;
reg [3:0] c;
// Outputs
wire [3:0] y;
// Instantiate the UUT
mul3_1_casez uut (.y(y)
www.eeworm.com/read/17937/767670
tf reg4_nbp_tb.tf
module testbench();
// DATE: Thu May 01 10:38:03 2003
// TITLE:
// MODULE: reg4_bpa
// DESIGN: reg4_bpa
// FILENAME: reg4_bpa
// PROJECT: reg4
// VERSION: Version 1.0
www.eeworm.com/read/17937/767674
tf mut4_2_1tb.tf
module testbench();
// Inputs
reg s;
reg [3:0] a;
reg [3:0] b;
// Outputs
wire [3:0] y;
// Instantiate the UUT
mul4_2_1 mul4_2_1tb (
.y(y),
.s(
www.eeworm.com/read/17937/767680
tf reg4_bpa_tb.tf
module testbench();
// DATE: Thu May 01 10:38:03 2003
// TITLE:
// MODULE: reg4_bpa
// DESIGN: reg4_bpa
// FILENAME: reg4_bpa
// PROJECT: reg4
// VERSION: Version 1.0
www.eeworm.com/read/18278/782904
vhd rcvr_tb.vhd
-- VHDL Test Bench Created from source file rcvr.vhd -- 17:36:24 04/12/2000
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_ve