reg4_bpa_tb.tf

FPGA开发板上写的Verilog代码 功能是从电脑端发送一个字节

module testbench();

// DATE:     Thu May 01 10:38:03 2003 
// TITLE:    
// MODULE:   reg4_bpa
// DESIGN:   reg4_bpa
// FILENAME: reg4_bpa
// PROJECT:  reg4
// VERSION:  Version 1.0


// Inputs
    reg CLK;
    reg RESET;
    reg Din;


// Outputs
    wire [3:0] Qout;


// Instantiate the UUT
    reg4_bpa reg4 (
        .Qout(Qout), 
        .CLK(CLK), 
        .RESET(RESET), 
        .Din(Din)
        );

initial
 $monitor ($time, "Data in=%b,  CLK=%b,  RESET=%b, Qout=%b", Din, CLK, RESET, Qout);

initial	//Initialize input signals
 begin
    CLK = 0;
    RESET = 1;
    Din = 0;
 end

initial 
 begin
   #35  RESET=0;	         //Disable RESET at 35 ns
   #50  Din = 1;             //Set Din at different times
   #150 Din = 0;
   #75  Din = 1;
 end

always #10 CLK=~CLK;	    //Set clock with a period 20 ns

initial #400 $finish;        //Complete simulation after 400 ns
  
endmodule