text_bench.v

以前在学校里的课程设计

module testbench;
   parameter width=8;
   wire  [width-1:0] address_out;
   wire [width-1:0] data_cm_bus;
   wire  S;
   wire  R;
   wire  D;
   
   reg clk;
   reg reset;
   
   mainboard  b  (.data_inout(data_cm_bus),.address_out(address_out),.S(S),.R(R),.D(D),.clk(clk),.reset(reset));
   memory     m  (.mem_data(data_cm_bus),.mem_address(address_out),.S(S),.R(R),.D(D)); 
     
   initial
     begin
       $monitor($time,"ALU_C=%d,mem_in=%d,mem[255]=%d,mem_data=%d,data_inout=%d,IR_out=%b,S=%b,D=%h,mem_address=%h,mem_out=%h,data_bus=%h,AC=%h,AR=%d,AB_sel=%b,IR=%d,PC=%d,state=%d,mux_DB_sel=%b,mem[%d]=%h,GR[%d]=%h,ALU=%h,GR_address=%d,GR_out=%h,GR[1]=%h,GR[0]=%h,c=%b,Z=%b",
                b.ALU_C,m.mem_in,m.mem[255],m.mem_data,b.data_inout,b.IR_out,m.S,m.D,m.mem_address,m.mem_out,b.data_bus,b.AC.register_out,b.AR.register_out,b.mux_AB_sel,b.IR.register_out,b.PC.pc_out,b.CU.state,b.mux_DB_sel,
                b.AR.register_out,m.mem[0],b.IR.register_out[2:0],b.GR.GR_out,b.ALU.ALU_O,b.GR.GR_address,b.GR.GR_out,b.GR.register[1],b.GR.register[0],b.C.register_out,b.Z.register_out);             	
        clk = 'b0;reset = 0;
         m.mem[100]=22;
         m.mem[108]=10;
         m.mem[0]=8'b00000_000;	//MOV AC,[100]
         m.mem[1]=100;
         m.mem[2]=8'b00011_000;	//MOV R0,AC
         m.mem[3]=8'b00000_001;
         m.mem[4]=108;
         m.mem[5]=8'b00011_001;//Mov R1,AC
         m.mem[6]=8'b00000_000;
         m.mem[7]=100;//AC=22,R1=10;R0=22;
         m.mem[8]=8'b01111_001;

         m.mem[9]=8'b11111_111;

 
         #1 reset=1;             	                                          
         #5000 $stop;    
   end

   always #50 clk = ~clk;

endmodule