memory.v

来自「以前在学校里的课程设计」· Verilog 代码 · 共 28 行

module memory(mem_data,mem_address,S,R,D);
   parameter width=8;
   
   inout [width-1:0] mem_data;	
   input [width-1:0] mem_address;  	
   input S,R,D;	
   
   wire[width-1:0] mem_in;
             
   reg   [width-1:0] mem_out;
   reg   [width-1:0] mem[255:0];


   assign mem_in = mem_data;
   assign mem_data = (S & D) ? mem_out : 'bz;
   
   always @(mem_in or mem_address or S or R or D)
      begin
	if(S)
	begin
	   if(D)
           	    mem_out <= mem[mem_address];
 	   if(R)
	        mem[mem_address] <= mem_in; 
        end
     end
endmodule