data_lock_test.vhd

本代码介绍了使用VHDL开发FPGA的一般流程

-- VHDL Test Bench Created from source file data_lock.vhd -- 21:22:03 12/13/2006
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY data_lock_data_lock_test_vhd_tb IS
END data_lock_data_lock_test_vhd_tb;

ARCHITECTURE behavior OF data_lock_data_lock_test_vhd_tb IS 

	COMPONENT data_lock
	PORT(
		OVER_in : IN std_logic;
		LOAD : IN std_logic;
		F : IN std_logic_vector(3 downto 0);
		E : IN std_logic_vector(3 downto 0);
		D : IN std_logic_vector(3 downto 0);
		C : IN std_logic_vector(3 downto 0);
		B : IN std_logic_vector(3 downto 0);
		A : IN std_logic_vector(3 downto 0);          
		OVER : OUT std_logic;
		BCD_6 : OUT std_logic_vector(3 downto 0);
		BCD_5 : OUT std_logic_vector(3 downto 0);
		BCD_4 : OUT std_logic_vector(3 downto 0);
		BCD_3 : OUT std_logic_vector(3 downto 0);
		BCD_2 : OUT std_logic_vector(3 downto 0);
		BCD_1 : OUT std_logic_vector(3 downto 0)
		);
	END COMPONENT;

	SIGNAL OVER_in :  std_logic;
	SIGNAL LOAD :  std_logic;
	SIGNAL F :  std_logic_vector(3 downto 0);
	SIGNAL E :  std_logic_vector(3 downto 0);
	SIGNAL D :  std_logic_vector(3 downto 0);
	SIGNAL C :  std_logic_vector(3 downto 0);
	SIGNAL B :  std_logic_vector(3 downto 0);
	SIGNAL A :  std_logic_vector(3 downto 0);
	SIGNAL OVER :  std_logic;
	SIGNAL BCD_6 :  std_logic_vector(3 downto 0);
	SIGNAL BCD_5 :  std_logic_vector(3 downto 0);
	SIGNAL BCD_4 :  std_logic_vector(3 downto 0);
	SIGNAL BCD_3 :  std_logic_vector(3 downto 0);
	SIGNAL BCD_2 :  std_logic_vector(3 downto 0);
	SIGNAL BCD_1 :  std_logic_vector(3 downto 0);

BEGIN

	uut: data_lock PORT MAP(
		OVER_in => OVER_in,
		LOAD => LOAD,
		F => F,
		E => E,
		D => D,
		C => C,
		B => B,
		A => A,
		OVER => OVER,
		BCD_6 => BCD_6,
		BCD_5 => BCD_5,
		BCD_4 => BCD_4,
		BCD_3 => BCD_3,
		BCD_2 => BCD_2,
		BCD_1 => BCD_1
	);


-- *** Test Bench - User Defined Section ***
   tb1 : PROCESS
   BEGIN
      OVER_in<='0';
	 wait for 50 ns;
	 OVER_in<='1';
	 wait for 100 ns;
   END PROCESS;

   tb2 : PROCESS
   BEGIN
      F<="0000";
	 E<="0001";
	 D<="0010";
	 C<="0011";
	 B<="0100";
	 A<="0101";
	 wait for 10 ns ;
	 F<="0101";
	 E<="0100";
	 D<="0011";
	 C<="0010";
	 B<="0001";
	 A<="0000";
	  wait for 10 ns ;
   END PROCESS;

   tb3 : PROCESS
   BEGIN
      LOAD<='0';
	 wait for 20 ns;
	 LOAD<='1';
	 wait for 10 ns;
	 LOAD<='0';
	 wait for 50 ns;
	 LOAD<='1';
	 wait for 10 ns;
	 LOAD<='0';
	 wait for 60 ns;
   END PROCESS;

-- *** End Test Bench - User Defined Section ***

END;