counter10_test.vhd

来自「本代码介绍了使用VHDL开发FPGA的一般流程」· VHDL 代码 · 共 63 行

-- VHDL Test Bench Created from source file counter10.vhd -- 09:47:06 12/15/2006
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY counter10_counter10_test_vhd_tb IS
END counter10_counter10_test_vhd_tb;

ARCHITECTURE behavior OF counter10_counter10_test_vhd_tb IS 

	COMPONENT counter10
	PORT(
		Reset : IN std_logic;
		CLK : IN std_logic;          
		carry_out : OUT std_logic;
		count_BCD_out : OUT std_logic_vector(3 downto 0)
		);
	END COMPONENT;

	SIGNAL Reset :  std_logic;
	SIGNAL CLK :  std_logic;
	SIGNAL carry_out :  std_logic;
	SIGNAL count_BCD_out :  std_logic_vector(3 downto 0);

BEGIN

	uut: counter10 PORT MAP(
		Reset => Reset,
		CLK => CLK,
		carry_out => carry_out,
		count_BCD_out => count_BCD_out
	);


-- *** Test Bench - User Defined Section ***
   tb1 : PROCESS
   BEGIN
      clk <= '1';
      wait for 10 ns;
      clk <= '0';
      wait for 10 ns;
   END PROCESS;
   tb2 : PROCESS
   BEGIN
      Reset <= '0';
      wait for 25 ns;
      Reset <= '1';
      wait for 625 ns;
      wait;
   END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;