代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/183930/9130113
v testbench.v
`timescale 10ms/10us
module testBench;
parameter T=1.667;
reg clk,reset;
digitalClock m(clk,reset,dispH1,dispH0,dispM1,dispM0,dispS1,dispS0);
initial
begin
clk=0;reset=0;
#T
www.eeworm.com/read/183929/9130129
v testbench.v
`define L_word 16
`timescale 10ns/100ps
module testBench;
wire [2*`L_word-1:0]product;
wire Ready;
reg [`L_word-1:0]word1,word2;
reg Start,clock,reset;
reg [2*`L_word-1:0] expected;
re
www.eeworm.com/read/182737/9193499
py testbench.py
######################################################################
#### ####
#### testbench.py
www.eeworm.com/read/376719/9309775
txt testbench.txt
writting <mark>testbench</mark>
入门级的还有XILINX的一篇文档how to write a <mark>testbench</mark>。
你看看这个，看思想。
如果说要看书的话，当然是“writting <mark>testbench</mark>”，是一本好书大书，英文的，要慢慢看。入门级的还有XILINX的一篇文档how to write a <mark>testbench</mark>。
主要是看看思想，本论坛中有好几篇不错的文章。你看看。
下面 ...
www.eeworm.com/read/375321/9364237
v testbench.v
`timescale 1 ns / 100 ps
//顶层测试激励文件
module tb;
parameter clk_period = 20; // changed by lgh
//input from sys
reg clk;
reg rst_n;
//sdram signal
wire sdram_cke;
wire sdra
www.eeworm.com/read/374138/9420438
v testbench.v
`include "params.v"
`define D_PER
/************************************************************************************/
module VD();
reg CLOCK;
initial CLOCK = 0;
always #(
www.eeworm.com/read/176580/9493338
dat testbench.dat
www.eeworm.com/read/176580/9493340
asm testbench.asm
www.eeworm.com/read/176580/9493358
vhd testbench.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity testshift is
end testshift;
architecture testbench of testshift is
component shift_register is
port ( Clk : in std_logic;
Rst : in std_logic
www.eeworm.com/read/372632/9499530
v testbench.v
///////////////////////////////////////////////////////////
// File: ucps_transm_top.v
// Version: V0.0
// Author: Jim Luo
// Date: 070904
// Company: SHHIC Co., Ltd.
//////