testbench.v

sdram 控制器的verilog 实现

`timescale 1 ns /  100 ps
//顶层测试激励文件
module tb;

parameter clk_period = 20;      // changed by lgh
//input from sys
reg 				clk;
reg 				rst_n;
//sdram signal
wire				sdram_cke;
wire				sdram_cs_n;
wire				sdram_ras_n;
wire				sdram_cas_n;
wire				sdram_we_n;
wire[1:0]			sdram_ba;
wire[1:0]			sdram_dqm;
wire[15:0]			sdram_data;   //note here
wire[11:0]			sdram_addr;

//----------------internal variable------------------------

//reg[15:0]   r_mem[0:15];	//declare the read  memory	

top top_inst(
								//input from sys
								.clk(clk),
								.rst_n(rst_n),
								
								.sdram_cke(sdram_cke),    // sdr clock enable
								.sdram_cs_n(sdram_cs_n),    // sdr chip select
								.sdram_ras_n(sdram_ras_n),  // sdr row address
								.sdram_cas_n(sdram_cas_n),  // sdr column select
								.sdram_we_n(sdram_we_n),    // sdr write enable
								.sdram_ba(sdram_ba),      // sdr bank address
								.sdram_dqm(sdram_dqm),	  // sdr dmq 
								.sdram_data(sdram_data),  // sdr data	
								.sdram_addr(sdram_addr)   // sdr address
						);					
//产生clk 50M    
initial
	begin
		clk=0;
    forever
		#(clk_period/2) clk = ~clk;
  end

initial 
	begin
    rst_n    = 1'b0;
	//应该对所有的reg信号进行初始化
	//对于没初始化的reg信号,默认值为不定态‘x’

	
 	repeat(10)
	@(negedge clk);
    rst_n    = 1'b1;
    $display("the rst_n signal invaild at time=%0dns",$time);

	#20000;
	$stop;
	
  end  					

endmodule