testbench.v

内含有完整的UART代码

///////////////////////////////////////////////////////////
// File:    ucps_transm_top.v
// Version: V0.0
// Author:  Jim Luo <[e-mail]>
// Date:    070904
// Company: SHHIC Co., Ltd.
////////////////////////////////////////////////////////////
// Description:
// This is the transmitting encryted data module file.
//
////////////////////////////////////////////////////////////
// Version: V0.1
// Modifier: name <email>
// Date:
// Description:
////////////////////////////////////////////////////////////

`timescale 1ns / 100ps
module testbench;

    reg	 clk_sys, clk_arm, clk_a, clk_v, rst, rst_n;
    reg  lrclk, mclk;
    reg	 de1, str, start;	
    reg  HSOUT_in1, VSOUT_in;
    reg  HSOUT_in, de;
    reg[13:0]	count1;
    reg[15:0]	count2;
    reg[23:0]	MEM1[193919:0];
    reg[3:0]	MEM2[14399:0];
    reg[31:0]   MEM3[7:0];

//    reg[3:0]    d_a;
    wire[3:0]    d_a;
    wire[23:0]	din;
    reg[30:0]	i;
    reg[25:0]   j;
    reg[11:0]   counter;
    reg	        state; 
    reg         alg_sel;
    reg         safe_en,  alg_en,  mod_sel,  state_sel;
    
    reg         data_aes_en;
    reg         read_aes_en;
    reg         read_aes_en1;
    reg[31:0]   arm_in;
//    wire[31:0]  arm_in;
    wire[31:0]  arm_in1;
    wire[31:0]  arm_in2;
    reg[3:0]    m;
    
    wire[7:0]   LED1;
    wire[7:0]   LED2;
/////////////////////////////////////////    
    wire                    Dout_clk1;        //output HDMI clock signal
    wire                    SCLK_out2;
    
    wire                    int1    ;
    wire                    int2    ;
    wire    [31:0]          arm_out1;
    wire    [31:0]          arm_out2;

    wire                    DE_out;
    wire    [23:0]          Dout_video;
    wire    [23:0]          Dout_video1;
    
    wire                    DE_out2;
    wire    [23:0]          Dout_video2;
    
    wire                    MCLK_out;
    wire                    LRCLK_out;
    wire                    SPDIF_out;
    wire    [3:0]           Dout_audio;    
    
    wire                    MCLK_out1;
    wire                    LRCLK_out1;
    wire                    SPDIF_out1;
    wire    [3:0]           Dout_audio1; 
    
    wire                    MCLK_out2;
    wire                    LRCLK_out2;
    wire                    SPDIF_out2;
    wire    [3:0]           Dout_audio2; 
    
    reg                     str_a;
    reg                     str_a1;
////////////////////////////////////////////    
    integer     FILEVOUT     ;
    integer     FILEAOUT     ;
    integer     FILEVOUT1     ;
    integer     FILEAOUT1     ;
    integer     FILEAES1     ;
    integer     FILEAES2     ;
    integer     FILEVOUT_PASS ;
    integer     FILEAOUT_PASS ;
    integer     FILEVOUT1_PASS;
    integer     FILEAOUT1_PASS;
    
    parameter   de_delay=101;
    parameter   dv_clk=10;
    parameter   dclk=5;
    parameter   da_clk=5000;
    parameter   dk=1;
                                 
  
top_en u1(
    .clk_arm(clk_arm),
    .clk_sys(clk_sys),
    .rst(rst),
    .Din_clk(clk_v), 
    .Din_video(din),
    .HSOUT_in(HSOUT_in),
    .VSOUT_in(VSOUT_in),
    .DE_in(de),
    .Din_audio(d_a),
    .MCLK_in(mclk),
    .LRCLK_in(lrclk),
    .SPDIF_in(1'b1),
    .SCLK_in(clk_a),
    
    .safe_en(safe_en),
    .alg_en(alg_en),
    .alg_sel(alg_sel),
    .mod_sel(mod_sel),
    .state_sel(state_sel),
    
    .data_aes_en(data_aes_en),
    .read_aes_en(read_aes_en),
    .data_aes_in(arm_in),
    
    .int(int1),    //interupt 
    .data_aes_out(arm_out1), 
    
    .LED(LED1),
    
    .Dout_clk(Dout_clk1),
    .Dout_video(Dout_video2),
    .HSOUT_out(HSOUT_out2),
    .VSOUT_out(VSOUT_out2),
    .DE_out(DE_out2),
    .Dout_audio(Dout_audio2),
    .MCLK_out(MCLK_out2),
    .LRCLK_out(LRCLK_out2),
    .SPDIF_out(SPDIF_out2),
    .SCLK_out(SCLK_out2)
    );
    
assign    DE_out1       =   DE_out2;
assign    HSOUT_out1    =   HSOUT_out2;
assign    VSOUT_out1    =   VSOUT_out2;
assign    Dout_video1   =   Dout_video2;
assign    Dout_audio1   =   Dout_audio2;
assign    MCLK_out1     =   MCLK_out2;
assign    LRCLK_out1    =   LRCLK_out2;
assign    SPDIF_out1    =   SPDIF_out2;

top_un u2(
    .clk_arm(clk_arm),
    .clk_sys(~clk_sys),
    .rst(rst),
    .Din_clk(clk_v), 
    .Din_video(Dout_video1),
    .HSOUT_in(HSOUT_out1),
    .VSOUT_in(VSOUT_out1),
    .DE_in(DE_out1),
    .Din_audio(Dout_audio1),
    .MCLK_in(MCLK_out1),
    .LRCLK_in(LRCLK_out1),
    .SPDIF_in(SPDIF_out1),
    .SCLK_in(clk_a),
    
    .safe_en(safe_en),
    .alg_en(alg_en),
    .alg_sel(alg_sel),
    .mod_sel(mod_sel),
    .state_sel(state_sel),
    
    .data_aes_en(data_aes_en),
    .read_aes_en(read_aes_en),
    .data_aes_in(arm_in),
    
    .int(int2),    //interupt 
    .data_aes_out(arm_out2),
    
    .LED(LED2),
    
    .Dout_clk(Dout_clk),
    .Dout_video(Dout_video),
    .HSOUT_out(HSOUT_out),
    .VSOUT_out(VSOUT_out),
    .DE_out(DE_out),
    .Dout_audio(Dout_audio),
    .MCLK_out(MCLK_out),
    .LRCLK_out(LRCLK_out),
    .SPDIF_out(SPDIF_out),
    .SCLK_out(SCLK_out)
    );
       
initial                             
       begin			    // video and audio clk testbench
	    clk_sys=1'b1;
	    clk_arm=1'b1;                   
	    clk_v=1'b1;                 
	    clk_a=1'b1;                 
	    lrclk=1'b1;
	    #100    mclk=1'b1;
       end
       
        always #dclk        clk_sys=~clk_sys;   //system clock
        always #dv_clk      clk_v=~clk_v;       //outside video clock
        always # dclk       clk_arm=~clk_arm;
        always #da_clk      clk_a=~clk_a;//outside audio clock
        always #(4*da_clk)  lrclk=~lrclk;//audio left/right signal
        always #(2*da_clk)  mclk=~mclk;  //audio output reference clock
         
initial 
       begin			    //testbench
			    str=1'b0;
	  #(290*10)	str=1'b1;
       end 

initial 
       begin			    //testbench
			    state_sel=1'b0;
//	  #60   	state_sel=1'b1;
       end 

initial 
       begin			    //testbench
			    safe_en=1'b0;
	  #60   	safe_en=1'b1;
       end 
     
initial 
	begin			     //testbench
	  de1=1'b0;
	  # ((290+20*2200+192)*10) repeat(10)
	  begin
	  repeat(540)
	  begin
	  #(280*20)   de1=1'b1;
	  #(1920*20)  de1=1'b0;
	  end
	  #(44000*20) de1=1'b0;	  
	  end
	end
	
initial 
	begin			     //testbench
	        start=1'b0;
	  #20   start=1'b1;
	  #10   start=1'b0;
	end
           
initial 
        begin                        //testbench
                 alg_sel=1'b0;
//          #60    alg_sel=1'b1;
        end
        
initial 
        begin                        //testbench
                 mod_sel=1'b0;
//          #60    mod_sel=1'b1;
        end
	   
initial 
	begin			     //testbench
	        rst=1'b1;
	  #15   rst=1'b0;
	end
	
initial 
	begin			     //testbench
	        rst_n=1'b0;
	  #15   rst_n=1'b1;
	end	

initial
     begin
             $readmemh   ("./result_v/data.txt", MEM1);
             $readmemh   ("./result_a/audio_data.txt", MEM2);
     end

initial
fork
    FILEVOUT     <= $fopen("./result_v/VideoOut.txt");
    FILEAOUT     <= $fopen("./result_a/AudioOut.txt");
    FILEVOUT1    <= $fopen("./result_v/VideoOut1.txt");
    FILEAOUT1    <= $fopen("./result_a/AudioOut1.txt");
join

initial
fork
    FILEVOUT_PASS     <= $fopen("./result_pass_v/VideoOut.txt");
    FILEAOUT_PASS     <= $fopen("./result_pass_a/AudioOut.txt");
    FILEVOUT1_PASS    <= $fopen("./result_pass_v/VideoOut1.txt");
    FILEAOUT1_PASS    <= $fopen("./result_pass_a/AudioOut1.txt");
join

always @(posedge clk_v)
begin
    if (DE_out==1 && state_sel==1)
        $fwrite(FILEVOUT,"%h\n",Dout_video);
end

always @(posedge clk_v)
begin
    if (DE_out2==1 && state_sel==1)
        $fwrite(FILEVOUT1,"%h\n",Dout_video2);
end

always @(posedge clk_a)
begin
    if (str_a1 && state_sel==1)
        $fwrite(FILEAOUT1,"%h\n",Dout_audio2);
end

always @(posedge clk_a)
begin
      if(str_a && state_sel==1)
        $fwrite(FILEAOUT,"%h\n",Dout_audio);
end
///////////////PASS mode result data
always @(posedge clk_v)
begin
    if (DE_out==1 && state_sel==0)
        $fwrite(FILEVOUT_PASS,"%h\n",Dout_video);
end

always @(posedge clk_v)
begin
    if (DE_out2==1 && state_sel==0)
        $fwrite(FILEVOUT1_PASS,"%h\n",Dout_video2);
end

always @(posedge clk_a)
begin
    if (str_a1 && state_sel==0)
        $fwrite(FILEAOUT1_PASS,"%h\n",Dout_audio2);
end

always @(posedge clk_a)
begin
      if(str_a && state_sel==0)
        $fwrite(FILEAOUT_PASS,"%h\n",Dout_audio);
end

initial 
	begin			     //testbench
	        str_a=1'b0;
	  #180000   str_a=1'b1;
	end

initial 
	begin			     //testbench
	        str_a1=1'b0;
	  #100000   str_a1=1'b1;
	end


	
always @(posedge clk_v or negedge rst_n)
     if(rst_n==0)
            count1	<=	0;
     else if(str==1 && de1==0 && count1 < 14'd2200)
	        count1	<=	count1	+	1;
          else 
            begin
            if(count1==14'd2200)
          	count1	<=	1;
            else
          	count1	<=	0;
	    end
	    
always @(posedge clk_v or negedge rst_n)
     if(rst_n==0)
            count2	<=	0;
     else if(str==1 && de1==0 && count2 < 16'd44280)
	        count2	<=	count2	+	1;
          else 
            begin
          if(count2==14'd44280)
          	count2	<=	1;
          else
          	count2	<=	0;
	        end	    
	    
always @(posedge clk_v or negedge rst_n)
     if(rst_n==0)
       HSOUT_in1	<=	0;
     else
     	begin
	if(str==1 && count1>=11'd88 && count1<11'd132)
	   HSOUT_in1	<=	1;
	else
	   HSOUT_in1	<=	0;
	end
	     	
always @(posedge clk_v or negedge rst_n)
     if(rst_n==0)
       begin
       de   	<=	0;
       HSOUT_in	<=	0;
       end
     else
       begin
       de	    <=	str & de1;//str & 
       HSOUT_in	<=	str & HSOUT_in1;//str & 
       end
     
always @(posedge clk_v or negedge rst_n)
     if(rst_n==0)
       VSOUT_in	<=	0;
     else
     	begin
	if(count2>=16'd4488 && count2<16'd15488)
	   VSOUT_in	<=	1;
	else
	   VSOUT_in	<=	0;
	end

always @(posedge clk_v or negedge rst_n)
    if(rst_n==0)
       i	<=	0;
     else
     	begin
     	if(de==1)
	    i	<=	i+1;
	    else
        i	<=	i;
	end
assign din  =   (de==1) ? MEM1[i]:0;
     
always @(posedge clk_a or negedge rst_n)
    if(rst_n==0)
            j	<=	0;
     else
     	begin
//        if(str==1)
	        j	<=	j+1;
//	    else
//	        j	<=	0;
	    end
assign       d_a	=	(alg_sel==0)?MEM2[j]:0;
//always @(posedge clk_a or negedge rst_n)
//    if(rst_n==0)
//       d_a	<=	0;
//     else
//     	begin    	
////	    #9980    d_a	<=	MEM2[j-1];
//            d_a	<=	MEM2[j-1];
//	    end
    

always @(posedge clk_v or	negedge	rst_n)
  begin
    if(rst_n==0)
      begin
	    counter	   <= #1 0;
	    state		<= #1  1'b0;
      end
    else
      begin
	if((de==1) &&(counter<=	11'd1920) )
	  begin
	    state	    <= #1  1'b0;
	    counter    <= #1 counter + 1;
	  end
	else 
	  begin
	    state	    <= #1  1'b1;
	    counter    <= #1 12'd0;
	  end	     
      end
  end

    initial $monitor($time,,,"din=%h d_a=%h Dout_video=%h Dout_audio=%h arm_out2=%h", din,d_a, Dout_video, Dout_audio, arm_out2);
///////////////////////////////////////////////AES128 testbench
    initial 
       begin                        //testbench
               data_aes_en=1'b0;
          #20  data_aes_en=1'b1;
          #10  data_aes_en=1'b0;
          #10  data_aes_en=1'b1;
          #10  data_aes_en=1'b0;
          #30  data_aes_en=1'b1;
          #10  data_aes_en=1'b0;
          #20  data_aes_en=1'b1;
          #10  data_aes_en=1'b0;
//          #10  data_aes_en=1'b1;
//          #10  data_aes_en=1'b0;
//          #30  data_aes_en=1'b1;
//          #10  data_aes_en=1'b0;
//          #10  data_aes_en=1'b1;
//          #10  data_aes_en=1'b0;
//          #30  data_aes_en=1'b1;
//          #10  data_aes_en=1'b0;//240
       end 

     initial 
       begin                        //testbench
              arm_in=32'h00000000;
          #20 arm_in=32'h2b7e1516;//aes_key=128'h2b7e151628aed2a6abf7158809cf4f3c;
          #20 arm_in=32'h28aed2a6;
          #40 arm_in=32'habf71588;
          #30 arm_in=32'h09cf4f3c;
//          #20 arm_in=32'h3243f6a8;//plain_txt=128'h3243f6a8885a308d313198a2e0370734;
//          #40 arm_in=32'h885a308d;
//          #20 arm_in=32'h313198a2;
//          #40 arm_in=32'he0370734;//cryption=39 25 84 1d 02 dc 09 fb dc 11 85 97 19 6a 0b 32;
       end 
    initial 
       begin                        //testbench
               read_aes_en=1'b0;
          #420 read_aes_en=1'b1;
          #10  read_aes_en=1'b0;
          #20  read_aes_en=1'b1;
          #10  read_aes_en=1'b0;
          #20  read_aes_en=1'b1;
          #10  read_aes_en=1'b0; 
          #20  read_aes_en=1'b1;
          #10  read_aes_en=1'b0;
       end  

    initial 
        begin                        //testbench
                 alg_en=1'b0;
          #240   alg_en=1'b1;
          #10    alg_en=1'b0;
        end

//always @(posedge clk_arm or negedge rst_n)
//    if(rst_n==0)
//       m	<=	0;
//     else
//     	begin
//     	if(data_aes_en==1)
//	    m	<=	m+1;
//	    else
//        m	<=	m;
//	end
//assign arm_in1  =   (data_aes_en==1) ? MEM3[m]:0;
//assign arm_in2  =   (data_aes_en==1) ? MEM3[m-1]:0;
//
//initial
//     begin
//             $readmemh   ("./result_aes128/aes_data.txt", MEM3);
//     end
//
initial
fork
    FILEAES1     <= $fopen("./result_aes128/aes_data1_Out.txt");
    FILEAES2     <= $fopen("./result_aes128/aes_data2_Out.txt");
join
//
//always @(posedge clk_arm or negedge rst_n)
//begin
//    if(rst_n==0)
//       read_aes_en1	<=	 0;
//    else
//       read_aes_en1 <=   read_aes_en;
//    
//end

always @(posedge clk_arm)
begin
    if (read_aes_en==1 && alg_sel==1)
        $fwrite(FILEAES1,"%h\n",arm_out1);
end

always @(posedge clk_arm)
begin
    if (read_aes_en==1 && alg_sel==1)
        $fwrite(FILEAES2,"%h\n",arm_out2);
end
    
endmodule