代码搜索：testbench
找到约 2,392 项符合「testbench」的源代码
代码结果 2,392
www.eeworm.com/read/224721/14570780
txt readme.txt
Directory: \simulation
This directory contains the vhdl testbench, associated files and the modelsim ini file for the
DDR SDRAM controller reference design. The \work directory contains a precom
www.eeworm.com/read/17963/768124
vhd tb_uart-tx.vhd
File Name : tb_tmp.vhd
-- This testbench was automatically generated
-- Filename : tb_tmp.vhd
-- Modelname : TB_UART_TX
-- Title :
-- Purpose
www.eeworm.com/read/17963/768201
vhd tb_uart_rx.vhd
File Name : tb_tmp.vhd
-- This testbench was automatically generated
-- Filename : tb_tmp.vhd
-- Modelname : TB_UART_RX
-- Title :
-- Purpose
www.eeworm.com/read/233917/4663534
v defs.v
// defs.v
//
// Globally visible typedefs for the CORDIC rotator model,
// bus interface and associated testbench
//
// Revision information:
// =====================
//
// 0.0 15-Jan-2004 J
www.eeworm.com/read/403299/2313107
v defs.v
// defs.v
//
// Globally visible typedefs for the CORDIC rotator model,
// bus interface and associated testbench
//
// Revision information:
// =====================
//
// 0.0 15-Jan-2004 J
www.eeworm.com/read/393840/8260404
txt readme.txt
Directory: \simulation
This directory contains the vhdl testbench, associated files and the modelsim ini file for the
DDR SDRAM controller reference design. The \work directory contains a precom
www.eeworm.com/read/103567/15728920
txt readme.txt
Directory: \simulation
This directory contains the vhdl testbench, associated files and the modelsim ini file for the
DDR SDRAM controller reference design. The \work directory contains a precom
www.eeworm.com/read/306496/13743579
80386_tb
:vpi_time_precision - 11;
:vpi_module "system";
S_003DFBD0 .scope module, "testbench" "testbench";
.timescale -9;
V_$00699C68 .var "clk", 0, 0;
V_$0069F5E0 .var "ins_len", 3, 0;
V_$0069F7C0 .va
www.eeworm.com/read/18102/774817
80386_tb
:vpi_time_precision - 11;
:vpi_module "system";
S_003DFBD0 .scope module, "testbench" "testbench";
.timescale -9;
V_$00699C68 .var "clk", 0, 0;
V_$0069F5E0 .var "ins_len", 3, 0;
V_$0069F7C0 .va
www.eeworm.com/read/359197/10161727
v ddr_sdram_tb.v
`timescale 1ns / 100ps
module ddr_sdram_tb();
// defines for the testbench
`define BL 8 // burst length
`define CL 3 //