ddr_sdram_tb.v

DDR（双速率）SDRAM控制器参考设计verilog代码

`timescale 1ns / 100ps

module ddr_sdram_tb();


// defines for the testbench
`define         BL              8               // burst length
`define         CL              3               // cas latency
`define         RCD             2               // RCD
`define         LOOP_LENGTH     1024            // memory test loop length


`include        "params.v"


reg                             clk;                    // Generated System Clock
reg                             clk2;                   // staggered system clock for sdram models

reg                             reset_n;                // Reset

reg     [2:0]                   cmd;                    // Command bus
reg     [`ASIZE-1:0]            addr;                   // Address
reg                             ref_ack;               
reg     [`DSIZE-1:0]            datain;
reg     [`DSIZE/8-1:0]          dm;


wire                            cmdack;
wire    [`DSIZE-1:0]            dataout;
wire    [11:0]                  sa;
wire    [1:0]                   ba;
wire    [1:0]                   cs_n;
wire                            cke;
wire                            ras_n;
wire                            cas_n;
wire                            we_n;
wire    [`DSIZE/2-1:0]          dq;
wire    [`DSIZE/16-1:0]         dqm;
wire    [`DSIZE/16-1:0]         dqs;

reg     [`DSIZE-1:0]            test_data;
reg     [`ASIZE-1:0]            test_addr;
reg     [11:0]                  mode_reg;


integer                         j;
integer                         x,y,z;
integer                         bl;


//instantiate the controller
ddr_sdram ddr_sdram1 (
                .CLK(clk),
                .RESET_N(reset_n),
                .ADDR(addr),
                .CMD(cmd),
                .CMDACK(cmdack),
                .DATAIN(datain),
                .DATAOUT(dataout),
                .DM(dm),
                .SA(sa),
                .BA(ba),
                .CS_N(cs_n),
                .CKE(cke),
                .RAS_N(ras_n),
                .CAS_N(cas_n),
                .WE_N(we_n),
                .DQ(dq),
                .DQM(dqm),
                .DQS(dqs)
                );

// instantiate the memory models
mt46v4m16 mem000      (.Dq(dq[15:0]),
                        .Dqs(dqs[0]),
                        .Addr(sa[11:0]),
                        .Ba(ba),
                        .Clk(clk2),
                        .Clk_n(!clk2),
                        .Cke(cke),
                        .Cs_n(cs_n[0]),
                        .Cas_n(cas_n),
                        .Ras_n(ras_n),
                        .We_n(we_n),
                        .Dm(dqm[1:0]));

mt46v4m16 mem001      (.Dq(dq[31:16]),
                        .Dqs(dqs[1]),
                        .Addr(sa[11:0]),
                        .Ba(ba),
                        .Clk(clk2),
                        .Clk_n(!clk2),
                        .Cke(cke),
                        .Cs_n(cs_n[0]),
                        .Cas_n(cas_n),
                        .Ras_n(ras_n),
                        .We_n(we_n),
                        .Dm(dqm[3:2]));

mt46v4m16 mem010      (.Dq(dq[47:32]),
                        .Dqs(dqs[2]),
                        .Addr(sa[11:0]),
                        .Ba(ba),
                        .Clk(clk2),
                        .Clk_n(!clk2),
                        .Cke(cke),
                        .Cs_n(cs_n[0]),
                        .Cas_n(cas_n),
                        .Ras_n(ras_n),
                        .We_n(we_n),
                        .Dm(dqm[5:4]));

mt46v4m16 mem011      (.Dq(dq[63:48]),
                        .Dqs(dqs[3]),
                        .Addr(sa[11:0]),
                        .Ba(ba),
                        .Clk(clk2),
                        .Clk_n(!clk2),
                        .Cke(cke),
                        .Cs_n(cs_n[0]),
                        .Cas_n(cas_n),
                        .Ras_n(ras_n),
                        .We_n(we_n),
                        .Dm(dqm[7:6]));

mt46v4m16 mem100      (.Dq(dq[15:0]),
                        .Dqs(dqs[0]),
                        .Addr(sa[11:0]),
                        .Ba(ba),
                        .Clk(clk2),
                        .Clk_n(!clk2),
                        .Cke(cke),
                        .Cs_n(cs_n[1]),
                        .Cas_n(cas_n),
                        .Ras_n(ras_n),
                        .We_n(we_n),
                        .Dm(dqm[1:0]));

mt46v4m16 mem101      (.Dq(dq[31:16]),
                        .Dqs(dqs[1]),
                        .Addr(sa[11:0]),
                        .Ba(ba),
                        .Clk(clk2),
                        .Clk_n(!clk2),
                        .Cke(cke),
                        .Cs_n(cs_n[1]),
                        .Cas_n(cas_n),
                        .Ras_n(ras_n),
                        .We_n(we_n),
                        .Dm(dqm[3:2]));
mt46v4m16 mem110      (.Dq(dq[47:32]),
                        .Dqs(dqs[2]),
                        .Addr(sa[11:0]),
                        .Ba(ba),
                        .Clk(clk2),
                        .Clk_n(!clk2),
                        .Cke(cke),
                        .Cs_n(cs_n[1]),
                        .Cas_n(cas_n),
                        .Ras_n(ras_n),
                        .We_n(we_n),
                        .Dm(dqm[5:4]));
mt46v4m16 mem111      (.Dq(dq[63:48]),
                        .Dqs(dqs[3]),
                        .Addr(sa[11:0]),
                        .Ba(ba),
                        .Clk(clk2),
                        .Clk_n(!clk2),
                        .Cke(cke),
                        .Cs_n(cs_n[1]),
                        .Cas_n(cas_n),
                        .Ras_n(ras_n),
                        .We_n(we_n),
                        .Dm(dqm[7:6]));

initial begin
        clk = 1;                        // initialize clocks
        clk2 = 1;
        reset_n = 0;                    // do a reset
        #100 reset_n = 1;
end

always begin
        #3 clk2 = ~clk2;
        #2 clk = ~clk;
end

//      write_burst(address, start_value, data_mask, RCD, BL)
//
//      This task performs a write access of size burst_length 
//      at SDRAM address to the SDRAM controller
//
//      address         : 	Address in SDRAM to start the burst access
//      start_value     :     Starting value for the burst write sequence.  The write burst task
//                              simply increments the data values from the start_value.
//      data_mask       :     Byte data mask for all cycles in the burst
//      RCD             :     RAS to CAS delay as programmed into the controller.
//      BL              :     Burst length

task    burst_write;
	
        input [`ASIZE-1   : 0]    address;
        input [`DSIZE-1   : 0]    start_value;
        input [`DSIZE/8-1 : 0]    data_mask;
        input [1 : 0]             RCD;
        input [3 : 0]             BL;

        integer                 i;

        begin
                addr <= address;                  // Assert the address
                cmd  <= 3'b010;                   // Assert the WRITEA command
                datain <= start_value;            // Setup the first data and 
                dm     <= data_mask;              //   data mask value
                @(cmdack==1);                     // Wait for ACK from controller
                cmd  <= 3'b000;                   // issue a NOP after the ack
                for (i=1 ; i<=(RCD-1); i=i+1)     // Wait until RCD has expired before clocking
                @(posedge clk);                   // data into the controller
                for(i = 1; i <= BL; i = i + 1)    
                begin
                        #2;
                        datain <= start_value + i;     // clock the data in
                        #2;
                        @(posedge clk);
                       
                end
                dm <= 0;	
        end
endtask



//      burst_read(address, start_value, CL, RCD, BL)
//
//      This task performs a read access of size burst_length 
//      at SDRAM address to the SDRAM controller
//
//      address         :       Address in SDRAM to start the burst access
//      start_value     :       Starting value for the burst write sequence.  The write burst task
//                              simply increments the data values from the start_value.
//      CL              :       CAS latency
//      RCD             :       RAS to CAS delay as programmed into the controller
//      BL              :       Burst Length

task    burst_read;
	
        input   [`ASIZE-1 : 0]	     address;
        input   [`DSIZE-1 : 0]          start_value;
        input   [2 : 0]                 CL;
        input   [1 : 0]                 RCD;
        input   [3 : 0]                 BL;
        integer                         i;
        integer                         ddr_cl;
        reg     [`DSIZE-1 : 0]          read_data;