tb_uart-tx.vhd

UART-FPGA完全好用的程序，ISE8.2下打开

File Name : tb_tmp.vhd



-- This testbench was automatically generated


-- Filename          : tb_tmp.vhd
-- Modelname         : TB_UART_TX
-- Title             :
-- Purpose           :
-- Author(s)         : root
-- Comment           :
-- Assumptions       :
-- Limitations       :
-- Known errors      :
-- Specification ref :
-- ------------------------------------------------------------------------
-- Modification history:
-- ------------------------------------------------------------------------
-- Version  | Author | Date       | Changes made
-- ------------------------------------------------------------------------
-- 1.0      | root | 24.010.2008 | inital version


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity TB_UART_TX is
end TB_UART_TX;

architecture BEH of TB_UART_TX is

   component UART_TX

      generic(DBIT      : integer  := 8 ;
              SB_TICK   : integer  := 16 );

      port(CLK            : in std_logic ;
           RESET          : in std_logic ;
           TX_START       : in std_logic ;
           S_TICK         : in std_logic ;
           DIN            : in std_logic_vector ( 7 downto 0 );
           TX_DONE_TICK   : out std_logic ;
           TX             : out std_logic );

   end component;


   constant PERIOD : time := 10 ns;

   signal W_CLK            : std_logic  := '0';
   signal W_RESET          : std_logic ;
   signal W_TX_START       : std_logic ;
   signal W_S_TICK         : std_logic ;
   signal W_DIN            : std_logic_vector ( 7 downto 0 );
   signal W_TX_DONE_TICK   : std_logic ;
   signal W_TX             : std_logic ;

begin

   DUT : UART_TX

      generic map(DBIT      => 8 ,
                  SB_TICK   => 16 )

      port map(CLK            => W_CLK,
               RESET          => W_RESET,
               TX_START       => W_TX_START,
               S_TICK         => W_S_TICK,
               DIN            => W_DIN,
               TX_DONE_TICK   => W_TX_DONE_TICK,
               TX             => W_TX);

   W_CLK <= not W_CLK after PERIOD/2;

   STIMULI : process
   begin
      W_RESET          <= '0';
      W_TX_START       <= '0';
      W_S_TICK         <= '0';
      W_DIN            <= (others => '0');

      wait for PERIOD;
      wait;
   end process STIMULI;

end BEH;

configuration CFG_TB_UART_TX of TB_UART_TX is
   for BEH
   end for;
end CFG_TB_UART_TX;




File Name : tb_tmp.ini



comm traces
   cd /TB_UART_TX/DUT
   trace CLK
   trace RESET
   trace TX_START
   trace S_TICK
   trace DIN
   trace TX_DONE_TICK
   trace TX
end

traces
run 1000




File Name : SIM_tb_tmp




vhdldbx -i tb_tmp.ini CFG_TB_UART_TX &