readme.txt

来自「基于VHDL编写的DDR-SDRAM控制器的编程」· 文本 代码 · 共 9 行

Directory: \simulation

This directory contains the vhdl testbench, associated files and the modelsim ini file for the 
DDR SDRAM controller reference design.  The \work directory contains a precompiled
library of the complete design.  In order to modify the design and re-simulate, simply
copy the source files from \source and \model into this directory and re-compile the
design.