代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/435259/7794915
vhd adjust.vhd
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ADJUST is
port (
MANSUM: in std_logic_vector (25 downto 0);
MANSFT: in std_logic_vector (
www.eeworm.com/read/435198/7795617
vhd vote7.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity vote7 is
port(a:in std_logic_vector(6 downto 0);
p,np:out std_logic);
end v
www.eeworm.com/read/435198/7795645
vhd renbjq.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity renbjq is
port(d:in std_logic_vector(6 downto 0);
green,red:out std_logic);
www.eeworm.com/read/435164/7796058
vhd sdr_sdram.vhd
--#######################################################################
--
-- LOGIC CORE: SDR SDRAM Controller
-- MODULE NAME: sdr_sdram()
-- COMPANY: Alte
www.eeworm.com/read/420203/7808895
vhd notetabs.vhd
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:39:05 01/10/2009
-- Design Name:
-- Module Name: NoteTabs -
www.eeworm.com/read/420203/7808942
vhd top .vhd
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:40:23 01/10/2009
-- Design Name:
-- Module Name: TOP - Beh
www.eeworm.com/read/299942/7819572
vhd addr.vhd
--addr (模块)正弦
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity addr is
port(
clk:in std_logic;
dout:out std_logic_vector(5 downto 0)
);
end ad
www.eeworm.com/read/299942/7819596
vhd sanjiao.vhd
--sanjiao 模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sanjiao is
port(
clk :in std_logic;
dout : out std_logic_vector(5 downto 0)
)
www.eeworm.com/read/299942/7819611
vhd updown2.vhd
-- updown2 模块(of testup_f_k)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity updown2 is
port(
r_in:in std_logic;
www.eeworm.com/read/299485/7847368
txt divide.txt
-----------compare
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity compare2 is
port(q:in std_logic_vector(8 downto 0);
b:in std_logic_vector(7 downto 0);