vote7.vhd

来自「实现7人表决功能」· VHDL 代码 · 共 26 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity vote7 is
port(a:in std_logic_vector(6 downto 0);
     p,np:out std_logic);
end vote7;
architecture behav of vote7 is
    signal i1,i2:std_logic_vector(2 downto 0);
begin
process(i2)
begin
    i1<="00"&a(0);
    i2<=i1+a(1)+a(2)+a(3)+a(4)+a(5)+a(6);

if i2<4 then
p<='0';
np<='1';
else
p<='1';
np<='0';
end if;
end process;
end behav;