divide.txt

除法器的设计本文所采用的除法原理是：对于八位无符号被除数A

-----------compare
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity compare2 is 
port(q:in std_logic_vector(8 downto 0);
     b:in std_logic_vector(7 downto 0);
     great_en:out std_logic);
end;
architecture one of compare2 is
 signal y:std_logic_vector(8 downto 0);
  begin
  y<='0'& b;
 process(q,y)
 variable check:std_logic;
  begin
  check:='1';
  if q=y then  great_en<='1';
   else
    for i in 8 downto 1 loop 
     if check='1' then 
      if(q(i)/=y(i)) then
       if ((q(i)='1') and (y(i)='0')) then great_en<='1'; check:='0';end if;
       if(q(i)='0' and y(i)='1' ) then great_en<='0'; check:='0';end if;
      else 
       if(q(i-1)/=y(i-1)) then
        if ((q(i-1)='1') and (y(i-1)='0')) then great_en<='1';check:='0'; end if;
        if(q(i-1)='0' and y(i-1)='1' ) then great_en<='0'; check:='0';end if;
       end if;
     end if;
    end if;
end loop;
   end if; 
end process;
end;
-----------clock



library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clock is 
port(clk,load:in std_logic;
     clkk,ariend:out std_logic);
end;
architecture one of clock is 
signal cnt:std_logic_vector(4 downto 0);
begin
process(clk,load)--产生16个脉冲
 begin
  if load='1' then cnt<="00000";
   elsif clk'event and clk='1' then
    if cnt<16 then cnt<=cnt+1; 
    end if;
  end if;
end process;
process(clk,cnt,load)
 begin
  if load='0' then 
   if cnt<16 then clkk<=clk; ariend<='0';
    else  clkk<='0';ariend<='1';
   end if;
 else clkk<=clk;
 end if;
end process;
end;















library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity divide is 
 port(clk,load:in std_logic;---clk为时钟信号,load为装载信号
      ariend:in std_logic;---ariend为运算结束信号
      ain,bin:in std_logic_vector(7 downto 0);--a为被除数,b为除数
      q,r:out std_logic_vector(7 downto 0));--q为商,r为余数
 end;
 
architecture one of divide is
 signal sign:std_logic_vector(15 downto 0);
 signal p,y: std_logic_vector(8 downto 0);---p为中间变量用于保存高17位数
 signal great_en:std_logic;
 begin

y<='0'&bin;

---移位模块
process(clk,load,ariend,great_en)
begin 
if clk'event and clk='1' then
  if ariend='0' then 
   if load='1'then 
    sign<="00000000"&ain(7 downto 0);
    else 
     if great_en='1' then 
      sign(15 downto 1)<=sign(14 downto 0);sign(0)<='1';
     else
      sign(15 downto 1)<=sign(14 downto 0);sign(0)<='0';
     end if;
     p<=sign(15 downto 7);
   end if;
 end if;
end if;
end process;
------

------减法电路

process(clk,great_en)
 variable y:std_logic_vector(8 downto 0);
 variable a: std_logic_vector(8 downto 0);
 begin
   if clk'event and clk='1' then
    if great_en='1' then 
     y:=not ('0'& bin);
     a:=p+y+1;---a为高17位与除数的差
    end if;
  sign(15 downto 7)<=a;
 end if;
end process;
---------

---------比较电路

process(p,y)
 variable check:std_logic;
  begin
  check:='1';
  if p=y then  great_en<='1';
   else
    for i in 8 downto 1 loop 
     if check='1' then 
      if(p(i)/=y(i)) then
       if ((p(i)='1') and (y(i)='0')) then great_en<='1'; check:='0';end if;
       if(p(i)='0' and y(i)='1' ) then great_en<='0'; check:='0';end if;
      else 
       if(p(i-1)/=y(i-1)) then
        if ((p(i-1)='1') and (y(i-1)='0')) then great_en<='1';check:='0'; end if;
        if(p(i-1)='0' and y(i-1)='1' ) then great_en<='0'; check:='0';end if;
       end if;
     end if;
    end if;
end loop;
   end if; 
end process;


---------
q<=sign(7 downto 0);
r<=sign(15 downto 8);


-----

end;