notetabs.vhd

门铃的VHDL程序

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:39:05 01/10/2009 
-- Design Name: 
-- Module Name:    NoteTabs - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
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-- Dependencies: 
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-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY NoteTabs IS                                            -- 顶层设计
    PORT (inclk : IN STD_LOGIC;                                 -- 音频分频信号
       ToneIndex : OUT STD_LOGIC_VECTOR (3 DOWNTO 0));        --音符译码输出            
END;

ARCHITECTURE one OF NoteTabs IS
COMPONENT MUSIC
   PORT ( addr :  IN STD_LOGIC_VECTOR(7 DOWNTO 0);
   clk  : IN STD_LOGIC;
   dout: OUT STD_LOGIC_VECTOR (3 DOWNTO 0));                        
END COMPONENT;

SIGNAL Counter : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
PROCESS(inclk)
BEGIN 
  IF Counter=138 THEN 
		Counter <="00000000";
  ELSIF (inclk'EVENT AND inclk = '1') THEN 
		COUNTER <= COUNTER + 1;
  END IF;
END PROCESS;
u1 : MUSIC PORT MAP(addr=>Counter, dout=>ToneIndex, clk=>inclk);
END;