top .vhd

门铃的VHDL程序

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:40:23 01/10/2009 
-- Design Name: 
-- Module Name:    TOP  - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


ENTITY TOP IS                                     -- 顶层设计
PORT (CLK12MHZ : IN STD_LOGIC;           -- 音频频率信号
		CLK8HZ : IN STD_LOGIC;             -- 节拍频率信号
		--INDEX1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);     -- 输入的音符信号
		CODE1 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);             --简谱码输出显示
      HIGH1,SPKOUT  : OUT STD_LOGIC   );--音符的高音表示
END TOP;
ARCHITECTURE one OF TOP IS

COMPONENT notetabs
	PORT ( inclk :  IN STD_LOGIC_VECTOR;
          ToneIndex : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
END COMPONENT;

COMPONENT Tonetaba
	PORT ( Index :  IN STD_LOGIC_VECTOR(3 DOWNTO 0);
          CODE : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
          HIGH1  : OUT STD_LOGIC; 
          Tone  : OUT INTEGER RANGE 0 TO 16#7FF#  ); --11位2进制数
END COMPONENT;

COMPONENT Speaker
   PORT (  clk  :  IN STD_LOGIC;
          Tone :  IN INTEGER RANGE 0 TO 16#7FF#;      --11位2进制数
          SpkS : OUT STD_LOGIC  );
END COMPONENT;

SIGNAL Tone : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL toneindex : STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN                    -- 安装U1, U2
u1 : Notetabs PORT MAP (inclk=>CLK8HZ, ToneIndex=>toneindex);
u2 : Tone PORT MAP (Index=>toneindex, Tone=>Tone,CODE=>CODE1,HIGH=>HIGH1);
u3 : Speaker PORT MAP (clk=>CLK12MHZ,Tone=>Tone, SpkS=>SPKOUT );
END;