代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/453028/7427876
vhd yimaqi.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
----------------------------------------
entity yimaqi is
port(F2,F1:in std_logic;
Y3,Y2,Y1,Y0:out std_logic);
e
www.eeworm.com/read/453028/7427880
vhd count16.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------
entity count16 is
port(clk:in std_logic;
D,C,B,A:out std_logi
www.eeworm.com/read/452301/7442151
vhd cfgtaddr_cardbus.vhd
--------------------------------------------------------------------------------
--
-- File : cfgtaddr_cardbus.vhd
-- Last Modification: 01/27/2004
--
-- Created In SpDE Version: SpDE 9.5.1
-- A
www.eeworm.com/read/452301/7442226
vhd r128x4_25um.vhd
------------------------------------------------------------------------
-- File : r128x4_25um.vhd
-- Design Date: June 9, 1998
-- Creation Date: Mon May 06 13:42:47 2002
-- Created By SpDE Vers
www.eeworm.com/read/452277/7442856
vhd count.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY COUNT IS
PORT(CLK,CLR,EN: IN STD_LOGIC;
S_1MS: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
S_10MS: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
S_100MS: OUT ST
www.eeworm.com/read/452277/7442893
vhd mb.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MB IS
PORT(SP,CLR,CLK:IN STD_LOGIC;
CO,EN: OUT STD_LOGIC;
LED: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
www.eeworm.com/read/452277/7443032
vhd count.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY COUNT IS
PORT(CLK,CLR,EN: IN STD_LOGIC;
S_1MS: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
S_10MS: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
S_100MS: OUT ST
www.eeworm.com/read/452277/7443070
vhd mb.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MB IS
PORT(SP,CLR,CLK:IN STD_LOGIC;
CO,EN: OUT STD_LOGIC;
LED: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
www.eeworm.com/read/452277/7443201
vhd mb.vhd
--1.顶层文件：mb.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mb is
port (
clk1,clk2: in STD_LOGIC;
clr
www.eeworm.com/read/452277/7443221
vhd dled.vhd
--顶层文件名：mb.VHD
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mb is
port (
clk1,clk2: in STD_LOGIC; ----引脚定义