yimaqi.vhd

来自「用VHDL语言实现TDMA编码,简单」· VHDL 代码 · 共 29 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
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entity yimaqi is
port(F2,F1:in std_logic;
     Y3,Y2,Y1,Y0:out std_logic);
end entity yimaqi;
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architecture rt1 of yimaqi  is
signal indata:std_logic_vector(1 downto 0);
signal Y:std_logic_vector(3 downto 0);
begin
indata<=F2&F1;
process(indata)
begin 
case indata is 
when"00"=>Y<="1110";
when"01"=>Y<="1101";
when"10"=>Y<="1011";
when"11"=>Y<="0111";
when others=>Y<="XXXX";
end case;
end process;
Y3<=Y(3);
Y2<=Y(2);
Y1<=Y(1);
Y0<=Y(0);
end rt1;