cfgtaddr_cardbus.vhd

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

--------------------------------------------------------------------------------
--
-- File : cfgtaddr_cardbus.vhd
-- Last Modification: 01/27/2004
--
-- Created In SpDE Version: SpDE 9.5.1
-- Author :	QuickLogic Corporation
-- Copyright (C) 2004, Licensed customers of QuickLogic may copy and modify
-- this file for use in designing with QuickLogic devices only.
--	
-- Description : This is a block in the QL5632-33 programmable logic region.
--	It contains 3 sections:
--		config space
--		target address register/counter
--		command decode
--
--	Main differences from QL5632 PCI configuration space
--	1.  PCI Command Register:  "Memory Space enable", "Parity Error Response", 
--		and "SERR# enable" bits are always implemented (ie not fixed).
--	2.	PCI Status Register:  "Signaled System Error", and "Detected Parity Error"
--		bits are always implemented (ie not fixed).
--	3.  QuickPCI already ignores "Interrupt Acknowledge" and "Dual Access Cycle" commands.
--	4.  Added CardBus_CIS:  CIS is set to be in memory space, starting at BAR5 offset 0.
--	 
--	 
-- Hierarchy:
--	This file represents the PCI Configuration Space block in the pci5632_208
--	schematic. Support is added for CardBus IP.
--
-- History:	
--	Date	        Author				Version
--  01/27/2004      Claire Pian Tu		1.0
--		- Initial release. Modifed from cfgtaddr_5632_280.vhd in 5632 ref design.
--
--------------------------------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cfgtaddr_5632_280_pkg.all;

entity cfgtaddr_cardbus is

generic (BAR0_size: integer := BAR0;
		 BAR5_size: integer := BAR5);    -- Sets the size of the requested memory space.
                                       --   Default value is 10, corresponding to 1KB.
                                       --   (# of bits to tie off in the BAR)
									   -- CT added BAR5

port ( -- config space ports
       CBE:         in  std_logic_vector(3 downto 0);
       Cfg_Write, PCI_clock: in std_logic;
	   CacheLineSizeReg: out std_logic_vector(7 downto 2);
       CmdReg:      out std_logic_vector(15 downto 0);
       WrData:      in  std_logic_vector(31 downto 0);
       MstPERR_Det, PERR_Det, TTO_Det: in std_logic;
       LatTimerReg: out std_logic_vector(7 downto 0);
       PCI_reset, SERR_Sig, Tabort_Det: in std_logic;
       CfgData:     out std_logic_vector(31 downto 0);  -- synthesis syn_preserve=1 
	   MstSC:		in std_logic;

       -- target address register/counter ports
       LoadAddr, IncrAddr: in std_logic;
       Addr_Hit, Usr_Stop: out std_logic;
       UsrAddr:     out std_logic_vector(BAR0_size-1 downto 0);
            -- the width of this port can be changed 
            -- if the size of the memory space is 
            -- changed (base addr reg)

	   -- CT added 
	   BAR0_Hit, BAR5_Hit : out std_logic;

       -- command decode ports
       Usr_RdCmd, Usr_WrCmd: out std_logic
       );

end cfgtaddr_cardbus;

architecture behavioral of cfgtaddr_cardbus is

    -- ************************
    -- ***   config space   ***
    -- ************************

    -- *** Full 32-bit wide PCI registers    offset
    signal Dev_Vend: std_logic_vector(31 downto 0);                -- 00h
    signal Stat_Cmd: std_logic_vector(31 downto 0);                -- 04h
    signal Class_RevID: std_logic_vector(31 downto 0);             -- 08h
    signal BIST_Hdr_Lat_Cache: std_logic_vector(31 downto 0);      -- 0Ch
    signal BAR0: std_logic_vector(31 downto 0);                    -- 10h
    signal BAR5: std_logic_vector(31 downto 0);                    -- 24h, CT for CIS
    signal SubsysID_SubsysVendID: std_logic_vector(31 downto 0);   -- 2Ch
    signal Lat_Gnt_IntPin_IntLine: std_logic_vector(31 downto 0);  -- 3Ch


    -- *** declarations for hard-wired and writable parameters

    -- *********** beginning of user-modifiable parameters ************

    -- PCI registers                          offset into config space
    constant DeviceID:      std_logic_vector(15 downto 0) := DeviceID; -- 0x001E, mem loc 00h 
    constant VendorID:      std_logic_vector(15 downto 0) := VendorID; -- 0x11E3, mem loc 00h
    constant ClassCode:     std_logic_vector(23 downto 0) := ClassCode; -- 0xFF0000, mem loc 08h Class Code Not Defined (FF)
    constant RevisionID:    std_logic_vector( 7 downto 0) := RevisionID;         -- 0x00,   mem loc 08h
    constant Cardbus_CIS:   std_logic_vector(31 downto 0) := CardBus_CIS;    -- 0x0000, mem loc 28h 
    constant SubsysID:      std_logic_vector(15 downto 0) := SubsysID; -- 0x0002, mem loc 2Ch
    constant SubsysVendID:  std_logic_vector(15 downto 0) := SubsysVendID; -- 0x11E3, mem loc 2Ch
    constant Expansion_ROM: std_logic_vector(31 downto 0) := Expansion_ROM;    -- 0x0000, mem loc 30h
    constant MaxLat:        std_logic_vector( 7 downto 0) := MaxLat;         -- 0x10,   mem loc 3Ch 8 clocks * MaxLat = Maximum Wait between Grants (128)
    constant MinGnt:        std_logic_vector( 7 downto 0) := MinGnt;         -- 0x08,   mem loc 3Ch 8 clocks * MinGnt = Minimum Burst Clocks Required (64)
    constant IntPin:        std_logic_vector( 7 downto 0) := IntPin;         -- 0x00,   mem loc 3Ch No Interrupts Used.  Set to "00000001" for INTA support.

    -- *********** end of user-modifiable parameters ************


    -- Command register (offset 04h) ................ bit
    constant IOEnable: std_logic := '0';                --   0   - always 0
    signal   MemEnable: std_logic;                      --   1   - FF - memory device, off by default until enabled
    signal   BusMasterEnable: std_logic;                --   2   - initiator enable
    signal   SpecialCycleEnable: std_logic;             --   3   - special cycles
    signal   MemWrAndInvalidateEnable: std_logic;       --   4   - mem write & invalidate
    constant VGAPaletteSnoopEnable: std_logic := '0';   --   5   - no palette snoop capability
    signal   ParityErrorEnable: std_logic;              --   6   - parity error enable
    constant WaitCycleControl: std_logic := '0';        --   7   - addr/data stepping never done
    signal   SERREnable: std_logic;                     --   8   - SERRn enable 
    constant FastBack2BackEnable: std_logic := '0';     --   9   - Fast back to back never done
                                                        -- 15-10 - reserved


    -- Status register (offset 04h) ...........  bit
    --                                               --  0-3  - reserved
	constant NewCapabilities: std_logic := '0';      --   4   - no new capabilities
    constant Capable66MHz: std_logic := '0';         --   5   - not 66MHz capable
    --                                               --   6   - reserved
    constant FastBack2BackCapable: std_logic := '1'; --   7   - target is fast back-to-back capable
    signal   DataParErrorDetected: std_logic;        --   8   - 
    constant DevselTiming: std_logic_vector(1 downto 0) := "01";  -- 10-9  - medium speed devsel assertion
	-- comment constant declaration and uncomment signal declaration for designs
	--     that are capable of generating target aborts
	-- signal   SignaledTargetAbort: std_logic;         --  11   - signaled target abort as target
    constant SignaledTargetAbort: std_logic := '0';  --  11   - target abort never generated
    signal   ReceivedTargetAbort: std_logic;         --  12   - 
    signal   ReceivedMasterAbort: std_logic;         --  13   - 
    signal   SignaledSystemError: std_logic;         --  14   - 
    signal   ParErrorDetected: std_logic;            --  15   - 


    -- registers at offset 0Ch
    constant HeaderType:    std_logic_vector(7 downto 0) := HeaderType;
    constant BIST:          std_logic_vector(7 downto 0) := BIST;
    signal   LatTimer:      std_logic_vector(7 downto 0);
    signal   CacheLineSize: std_logic_vector(7 downto 2);  -- needed for implementing Memory Write and Invalidate, must be at least 4

    -- base address registers (BAR's)
    signal   BAR0_reg:   std_logic_vector(31 downto BAR0_size);
    constant BAR0_lower: std_logic_vector(BAR0_size-1 downto 0) := (others => '0');

    -- CT for CIS
--    signal	CIS
    signal   BAR5_reg:   std_logic_vector(31 downto BAR5_size);
    constant BAR5_lower: std_logic_vector(BAR5_size-1 downto 0) := (others => '0');
			      
    -- registers at offset 3Ch
    -- Comment constant declaration and uncomment signal declaration for Interrupt Support
    -- signal IntLine: std_logic_vector(7 downto 0);
    constant IntLine: std_logic_vector(7 downto 0) := IntLine;

    -- Registered version of address for config address decodes
    signal cfgadr: std_logic_vector(3 downto 0);

    signal StatusRegWE: std_logic;
    signal CommandLoWE: std_logic;
    signal CommandHiWE: std_logic;
    signal LatTimerWE : std_logic;
	signal CacheLineSizeWE : std_logic;
    signal BAR0WE     : std_logic;
	-- CT for CIS
	signal BAR5WE	  : std_logic;
	signal BAR0_Hit_int : std_logic;
	signal BAR5_Hit_int : std_logic;
--	signal CIS_Hit_int : std_logic;
--	signal BAR5_latched : std_logic_vector(31 downto BAR5_size);
--    signal IntLineWE  : std_logic;
    signal UsrAddr_local: std_logic_vector(BAR0_size-1 downto 0) := (others => '0');

    constant ALL_ONES: std_logic_vector(BAR0_size-1 downto 2) := (others => '1');

begin
    UsrAddr <= UsrAddr_local;

    -- *** assignments that construct the 32-bit wide PCI config registers
    -- offset 00h
    Dev_Vend <= DeviceID & VendorID after 1 ns;

    -- offset 04h
    Stat_Cmd <= --status register
                ParErrorDetected    &
                SignaledSystemError &
                ReceivedMasterAbort &
                ReceivedTargetAbort &
                SignaledTargetAbort &
                DevselTiming(1 downto 0)   &
                DataParErrorDetected &
                FastBack2BackCapable &
                '0' & -- bit 6 is reserved
                Capable66MHz &
				NewCapabilities &
                "0000" & -- bits 3:0 reserved
                --command register:
                "000000" & -- bits 15:10 reserved
                FastBack2BackEnable &
                SERREnable &
                WaitCycleControl &
                ParityErrorEnable &
                VGAPaletteSnoopEnable &
                MemWrAndInvalidateEnable &
                SpecialCycleEnable &
                BusMasterEnable &
                MemEnable &
                IOEnable
                after 1 ns;

    -- offset 08h
    Class_RevID <= ClassCode & RevisionID after 1 ns;

    -- offset 0Ch
    BIST_Hdr_Lat_Cache <= BIST & HeaderType & LatTimer & CacheLineSize & "00" after 1 ns;

    -- offset 10h
    BAR0 <= BAR0_reg & BAR0_lower after 1 ns;

    -- CT for CIS, offset 24h
    BAR5 <= BAR5_reg & BAR5_lower after 1 ns;


    -- offset 2Ch
    SubsysID_SubsysVendID <= SubsysID & SubsysVendID after 1 ns;

    -- offset 3Ch
    Lat_Gnt_IntPin_IntLine <= MaxLat & MinGnt & IntPin & IntLine after 1 ns;

    -- *** assignments for the write-able registers and bits

    -- Status register, offset 04h

    StatusRegWE <= IncrAddr and Cfg_Write and not CBE(3) when cfgadr = "0001" else '0';

    process (PCI_clock, PCI_reset)