count.vhd

数字秒表具有正及时倒计时功能包括一些设计要求和原资料

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY COUNT IS
PORT(CLK,CLR,EN: IN STD_LOGIC;
S_1MS:    OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
S_10MS:   OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
S_100MS:  OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
S_1S:     OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
S_10S:    OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_1MIN:   OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_10MIN:  OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
HOUR:     OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COUNT;
ARCHITECTURE ART OF COUNT IS
 COMPONENT CDU10
     PORT(CLK,CLR,EN: IN STD_LOGIC;
             CN:      OUT STD_LOGIC;
         COUNT10:     OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT CDU10;
COMPONENT CDU6
     PORT(CLK,CLR,EN: IN STD_LOGIC;
          CN:         OUT STD_LOGIC;
          COUNT6:     OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT CDU6;
SIGNAL A,B,C,D,E,F,G,H:STD_LOGIC;
BEGIN
UL:CDU10  PORT  MAP(CLK,CLR,EN,A,S_1MS);
U2:CDU10  PORT  MAP(A,CLR,EN,B,S_10MS);
U3:CDU10  PORT  MAP(B,CLR,EN,C,S_100MS);
U4:CDU10  PORT  MAP(C,CLR,EN,D,S_1S);
U5:CDU6   PORT  MAP(D,CLR,EN,E,S_10S);
U6:CDU10  PORT  MAP(E,CLR,EN,F,M_1MIN);
U7:CDU6   PORT  MAP(F,CLR,EN,G,M_10MIN);
U8:CDU10  PORT  MAP(G,CLR,EN,H,HOUR);
END ART;