count16.vhd

来自「用VHDL语言实现TDMA编码,简单」· VHDL 代码 · 共 27 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------
entity count16 is
port(clk:in std_logic;
      D,C,B,A:out std_logic);
end entity count16;
--------------------------------------------------
architecture rt1 of count16 is
    signal count_4:std_logic_vector(3 downto 0);
begin
process(clk)
begin
 if(clk'event and clk='1')then
 if(count_4="1111") then
 count_4<="0000";
 else 
 count_4<=count_4+1;
end if;
end if;
end process;
D<=count_4(0);
C<=count_4(1);
B<=count_4(2);
A<=count_4(3);
end architecture rt1;