代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/456671/7342632
vhd instru_fetch.vhd
-- 取指部分instru_fetch
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--use work.exp_cpu_components.all;
entity instru_fetch is ----
www.eeworm.com/read/456114/7357359
vhd cnt100c.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT100C IS
PORT(LD,CLK,RST,EN:IN STD_LOGIC;
Q:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CQ:BUFFER STD_LOGIC_VECTOR(
www.eeworm.com/read/455332/7373224
txt time_24.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity time_24 is
port(clk ,clear: in std_logic;
cout1,cout2:buffer std_logic);
end;
architecture one of
www.eeworm.com/read/455332/7373229
vhd seltime.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity SELTIME is
port(
clk:in std_logic;
sec1,sec0,min1,min0,h1,h0:i
www.eeworm.com/read/455332/7373232
vhd hour.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity HOUR is
port(clk,en:in std_logic;
h1,h0:out std_logic_vector(3 downto 0));
end HOUR;
architecture hour_
www.eeworm.com/read/455332/7373233
vhd second.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity SECOND is
port(clk,clr:in std_logic;
sec1,sec0:out std_logic_vector(3 downto 0);
co:out std_logic);
www.eeworm.com/read/455332/7373234
vhd minute.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity MINUTE is
port(clk,en:in std_logic;
min1,min0:out std_logic_vector(3 downto 0);
co:out std_logic);
e
www.eeworm.com/read/455332/7373240
vhd seltime.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity SELTIME is
port(
clk:in std_logic;------扫描时钟
secm1,secm0,sec1,
www.eeworm.com/read/455332/7373242
vhd hour.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity HOUR is
port(clk,en:in std_logic;----输入时钟/高电平有效的使能信号
h1,h0:out std_logic_vector(3 downto 0));----时高位/低位
en
www.eeworm.com/read/455332/7373244
vhd second.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity SECOND is
port(clk,clr:in std_logic;----时钟/清零信号
sec1,sec0:out std_logic_vector(3 downto 0);----秒高位/低位