seltime.vhd

来自「关于数字钟的实现」· VHDL 代码 · 共 36 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity SELTIME is
  port(
        clk:in std_logic;
        sec1,sec0,min1,min0,h1,h0:in std_logic_vector(3 downto 0);
        daout:out std_logic_vector(3 downto 0);
        sel:out std_logic_vector(2 downto 0));
end SELTIME;
architecture fun of SELTIME is
   signal count:std_logic_vector(2 downto 0);
begin
   sel<=count;
   process(clk)
          begin
              if(clk'event and clk='1') then
                 if(count>="101") then
                    count<="000";
                  else
                    count<=count+1;
                  end if;
               end if;
  case count is
  when"000"=>daout<= sec0;
  when"001"=>daout<= sec1;
  when"010"=>daout<= min0;
  when"011"=>daout<= min1;
  when"100"=>daout<=h0;
  when others =>daout<=h1;
  end case;
  end process;
end fun;