cnt100c.vhd

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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT100C IS
	PORT(LD,CLK,RST,EN:IN STD_LOGIC;
		Q:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		CQ:BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0);
		COUT:OUT STD_LOGIC);
END CNT100C;

ARCHITECTURE BEHAV OF CNT100C IS
COMPONENT CNT10B
	PORT(LD,CLK,RST,EN:IN STD_LOGIC;
		Q:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
		CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
		COUT:OUT STD_LOGIC);
END COMPONENT;
COMPONENT AND2B
	PORT(A,B:IN STD_LOGIC;
		C:OUT STD_LOGIC);
END COMPONENT;

SIGNAL D,E,F,G,I:STD_LOGIC;

BEGIN
  F<=CQ(3);
  G<=CQ(0);
  U1:CNT10B PORT MAP(LD=>LD,CLK=>CLK,RST=>RST,EN=>EN,Q=>Q(3 DOWNTO 0),CQ=>CQ(3 DOWNTO 0),COUT=>D);
  U2:CNT10B PORT MAP(LD=>LD,CLK=>CLK,RST=>RST,EN=>I ,Q=>Q(7 DOWNTO 4),CQ=>CQ(7 DOWNTO 4),COUT=>E);
  U3:AND2B  PORT MAP( A=>D,B=>E,C=>COUT);
  U4:AND2B	PORT MAP( A=>F,B=>G,C=>I);
END ARCHITECTURE BEHAV;