instru_fetch.vhd

CPU代码-VHDL语言

-- 取指部分instru_fetch
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--use work.exp_cpu_components.all;

entity instru_fetch  is    -----
	port(reset,clk:	 in std_logic;
		lj_instruct: in std_logic; --长转移指令
		DW_intruct:	 in std_logic;  
		c_z_j_flag:  in std_logic; --为1时，进行条件转移
		sjmp_addr:	 in std_logic_vector(15 downto 0); --条件转移指令的转移地址
		data_read:	 in std_logic_vector(15 downto 0); --存储器读出的数，至于它连到哪，由顶层决定。
		t1,t2,t3: 		 buffer std_logic;   --周期/节拍   
		pc:			 buffer std_logic_vector(15 downto 0);
		pc_inc:		 buffer std_logic_vector(15 downto 0);
		IR:			 out std_logic_vector(15 downto 0)
		);
end instru_fetch;
		
architecture behav of instru_fetch is
signal start:	std_logic;

begin
IR_poc: process(reset,t2)
begin
	if reset = '0' then
		IR <= x"7000";  --nop指令
	elsif t2'event and t2 = '1' then   --- T2上升沿
		IR <= data_read;     ---来自memory-unit,他们之间的连接在顶层实现
	end if;
end process;

process(reset,clk)   ----产生T1/T2/T3分配节拍
begin
    if reset = '0' then
      start <= '1';
	else
		if clk'event and clk ='0' then
			start <= '0';
		end if;
	end if;
end process;

process(reset,clk)    ---- 产生T1、T2、T3节拍（即产生循环移位R），只要有clk触发（一般是连续），就会不断产生t1\t2\t3节拍

begin	
	if reset = '0' then
    	t1 <= '0';
        t2 <= '0';
		t3 <= '0';
	elsif clk'event and clk = '1' then   
		t1 <= start or t3;   
		t2 <= t1;
		t3 <= t2;
	end if;
end process;

pc_inc <= pc + '1';		--为取下一条指令做准备
PC_proc:	process(reset,t3)    ----给PC赋值
begin
   if reset = '0' then  
		pc <= x"0000";
	elsif t3'event and t3 = '0' then
		if lj_instruct = '1' then   ----"JMP ADR"指令
			pc <= data_read;
		elsif c_z_j_flag ='1' then
			pc <= sjmp_addr;
		elsif DW_intruct = '1' then
			pc <= pc + "10";  
		else
			pc <= pc_inc;
		end if;
	end if;
end process;

end behav;