decoder_4_to_16.vhd

来自「CPU代码-VHDL语言」· VHDL 代码 · 共 46 行

--4-16译码器decoder_4_to_16

library ieee;
use ieee.std_logic_1164.all;

entity decoder_4_to_16 is	
    port (
		 sel: 	in std_logic_vector(3 downto 0);
		 sel00: out std_logic;   
		 sel01: out std_logic;
		 sel02: out std_logic;
		 sel03: out std_logic;
		 sel04: out std_logic;   
		 sel05: out std_logic;
		 sel06: out std_logic;
		 sel07: out std_logic;
		 sel08: out std_logic;   
		 sel09: out std_logic;
		 sel10: out std_logic;
		 sel11: out std_logic;
		 sel12: out std_logic;   
		 sel13: out std_logic;
		 sel14: out std_logic;
		 sel15: out std_logic
		 );
end decoder_4_to_16;

architecture behavioral of decoder_4_to_16 is
begin
	sel00 <= (not sel(3)) and (not sel(2))and(not sel(1)) and (not sel(0));
	sel01 <= (not sel(3)) and (not sel(2))and(not sel(1)) and sel(0);
	sel02 <= (not sel(3)) and (not sel(2))and sel(1) and (not sel(0));  
	sel03 <= (not sel(3)) and (not sel(2))and sel(1) and sel(0);
	sel04 <= (not sel(3)) and sel(2)and(not sel(1)) and (not sel(0));
	sel05 <= (not sel(3)) and sel(2)and(not sel(1)) and sel(0);
	sel06 <= (not sel(3)) and sel(2)and sel(1) and (not sel(0));  
	sel07 <= (not sel(3)) and sel(2)and sel(1) and sel(0);
	sel08 <= sel(3) and (not sel(2))and(not sel(1)) and (not sel(0));
	sel09 <= sel(3) and (not sel(2))and(not sel(1)) and sel(0);
	sel10 <= sel(3) and (not sel(2))and sel(1) and (not sel(0));  
	sel11 <= sel(3) and (not sel(2))and sel(1) and sel(0);
	sel12 <= sel(3) and sel(2) and(not sel(1)) and (not sel(0));
	sel13 <= sel(3) and sel(2) and(not sel(1)) and sel(0);
	sel14 <= sel(3) and sel(2) and sel(1) and (not sel(0));  
	sel15 <= sel(3) and sel(2) and sel(1) and sel(0);
end behavioral;