📄 time_24.txt
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity time_24 is
port(clk ,clear: in std_logic;
cout1,cout2:buffer std_logic);
end;
architecture one of time_24 is
signal counter1: std_logic_vector(9 downto 0);
signal counter2: std_logic_vector(5 downto 0);
begin
process(clk,clear)
begin
if clear='1' then
counter1 <=(others=>'0');
counter2 <=(others=>'0');
elsif
clk'event and clk ='1' then
if counter1<"11111000111" then
counter1<=counter1 +1;
else
cout1<=not cout1;
end if;
if counter2<"110001" then
counter2<=counter2 +1;
else
cout2<=not cout2;
end if;
end if;
end process;
end one;
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