代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/417505/10987308
vhd shift register.vhd
library ieee;
use ieee.std_logic_1164.all;
Entity ShiftReg is
port(
s,clk1:in std_logic;
reset1:in std_logic;
Q2:out std_logic_vector(3 downto 0)
www.eeworm.com/read/417505/10987322
vhd counter.vhd
library ieee;
use ieee.std_logic_1164.all;
Entity Counter is
port(
clk1:in std_logic;
reset1:in std_logic;
Q2:out std_logic_vector(3 downto 0)
www.eeworm.com/read/417397/10991770
txt 计数器：generate语句的应用.txt
-- Generated Binary Up Counter
-- The first design entity is a T-type flip-flop.
-- The second is an scalable synchronous binary up counter illustrating the use of the generate statement to produce
www.eeworm.com/read/417397/10991806
txt 带load、clr等功能的寄存器2.txt
--
--
---------------------------------------------------------------------------------------
-- DESCRIPTION : Shift register
-- Type : univ
-- Width : 4
--
www.eeworm.com/read/271060/11010295
vhd miniuart.vhd
--===========================================================================--
--
-- S Y N T H E Z I A B L E miniUART C O R E
--
-- www.OpenCores.Org - January 2000
-- This core adheres
www.eeworm.com/read/271060/11010296
vhd miniuart.vhd
--===========================================================================--
--
-- S Y N T H E Z I A B L E miniUART C O R E
--
-- www.OpenCores.Org - January 2000
-- This core adheres
www.eeworm.com/read/271050/11010758
pkg string_plus.pkg
-- Source: T:/hwdev/generic/VHDL/string_plus.pkg
-- Designer: Tim Pagden
-- Description: Extensions to the std.standard.string package to allow
-- conversion functions and mixed operators
www.eeworm.com/read/271041/11010951
vhd control_fsm_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXXXX
www.eeworm.com/read/416784/11013409
vhd mux8.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity mux8 is
port(
a,b,c,d,e,f:in std_logic_vector(3 downto 0);
clk:in std_logi
www.eeworm.com/read/270913/11020601
vhd cnn.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnn is
port(clk :in std_logic;
dataout:out std_logic_vector(31 downto 0));
end cnn;
architecture aa