📄 mux8.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity mux8 is
port(
a,b,c,d,e,f:in std_logic_vector(3 downto 0);
clk:in std_logic;
sel:out std_logic_vector(7 downto 0);
q:out std_logic_vector(3 downto 0) );
end mux8;
architecture behave of mux8 is
signal other:std_logic_vector(3 downto 0);
begin
other <= "1010";
process(a,b,c,d,e,f,clk)
variable state: integer range 0 to 7;
begin
if(clk'event and clk='1') then
if(state=7) then
state:=0;
else
state:=state+1;
end if;
end if;
case state is
when 0 =>
q<=f;
sel<="00000001";
when 1 =>
q<=e;
sel<="00000010";
when 2 =>
q<=other;
sel<="00000100";
when 3 =>
q<=d;
sel<="00001000";
when 4 =>
q<=c;
sel<="00010000";
when 5 =>
q<=other;
sel<="00100000";
when 6 =>
q<=b;
sel<="01000000";
when 7 =>
q<=a;
sel<="10000000";
when others =>
q<="0000";
sel<="000000";
end case;
end process;
end behave;
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