counter.vhd

来自「vhdl codes for combinational and sequent」· VHDL 代码 · 共 38 行

library ieee;
    use ieee.std_logic_1164.all;
    Entity Counter is
        port(
            clk1:in std_logic;
            reset1:in std_logic;
            Q2:out std_logic_vector(3 downto 0)
            );
        end Counter;
        Architecture Bhv of Counter is 
        component JKFF is
            port(
                j,k:in std_logic;
                clk,reset:in std_logic;
                Q:out std_logic);
            End component;
            signal Q1:std_logic_vector(3 downto 0);
            signal t,t1:std_logic;
            begin
                t<='1';
                process(Q1)
                    begin
                        if Q1(0)='1' then
                            t1 <='1';
                            else
                            t1<='0';
                        end if;
                    end process;
                   -- reset1<=t1;
                U1:JKFF port map(t,t,clk1,reset1,Q1(0));
                U2:JKFF port map(t,t,Q1(0),reset1,Q1(1));
                U3:JKFF port map(t,t,Q1(1),reset1,Q1(2));
                U4:JKFF port map(t,t,Q1(2),reset1,Q1(3));
                Q2<=NOT(Q1);
                
            end Bhv;