cnn.vhd

fpga的应用

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnn is
  port(clk :in std_logic;
        dataout:out std_logic_vector(31 downto 0));
end cnn;
architecture aa of cnn is
--signal data:std_logic_vector(31 downto 0);
begin
process(clk)
  begin
    if clk'event and clk='1' then
        dataout<="00000100000110001001010011000000";
    else
        dataout<="00000100000110001001010011000000";
    end if;
end process;
end aa;