shift register.vhd

vhdl codes for combinational and sequential circuit

library ieee;
    use ieee.std_logic_1164.all;
    Entity ShiftReg is
        port(
            s,clk1:in std_logic;
            reset1:in std_logic;
            Q2:out std_logic_vector(3 downto 0)
            );
        end ShiftReg;
        Architecture Bhv of ShiftReg is 
        component JKFF is
            port(
                j,k:in std_logic;
                clk,reset:in std_logic;
                Q:out std_logic);
            End component;
            signal Q1:std_logic_vector(3 downto 0);
            signal t:std_logic;
            begin
                t<='1';
                U1:JKFF port map(s,t,clk1,reset1,Q1(0));
                U2:JKFF port map(Q1(0),t,clk1,reset1,Q1(1));
                U3:JKFF port map(Q1(1),t,clk1,reset1,Q1(2));
                U4:JKFF port map(Q1(2),t,clk1,reset1,Q1(3));
                Q2<=Q1;
            end Bhv;