代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/176100/9516622
vhd arith_lib.vhd
-------------------------------------------------------------------------------
-- Title : Library component declarations
-- Project : VHDL Library of Arithmetic Units
----------------------
www.eeworm.com/read/175784/9531229
vhd reg_exchange.vhd
--reg_exchange.vhd
--v0.1
--output measure
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity reg_exchange is
port(
clk: in std_logic;
reset: in std_log
www.eeworm.com/read/175784/9531358
vhd conv_213.vhd
--conv_213.vhd (2,1,3) juan ji ma of G=(111,101)
--v0.1
--06-10-2
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity conv_213 is
port(
clk: in std_logic;
www.eeworm.com/read/371886/9532080
vhd uarttest.vhd
--============================================================================--
-- Design units : TestBench for miniUART device.
--
-- File name : UARTTest.vhd
--
-- Purpose : Imp
www.eeworm.com/read/371618/9545444
bak fourbitincrement.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
entity fourbitincrement is
port(
a:in std_logic_vector(3 downto 0);
y:out std_logic_vector(6 downto 0)
);
end fourbitincrement;
arc
www.eeworm.com/read/371618/9545446
vhd fourbitincrement.vhd
library ieee;
use ieee.std_logic_1164.all;
entity fourbitincrement is
port(
a:in std_logic_vector(3 downto 0);
y:out std_logic_vector(3 downto 0)
);
end fourbitincrement;
arc
www.eeworm.com/read/371617/9545470
vhd lab7.vhd
library ieee;
use ieee.std_logic_1164.all;
entity lab7 is
port(
clk1: in std_logic;
ssega,ssegb,ssegc,ssegd:out std_logic_vector(6 downto 0)
);
end lab7;
architecture one of lab7 i
www.eeworm.com/read/371617/9545610
bak lab7.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
entity lab7 is
port(
clk1: in std_logic;
sseg0,sseg1,sseg2,sseg3:out std_logic_vector(6 downto 0)
);
end lab7;
architecture one of lab7 i
www.eeworm.com/read/175328/9552147
vhd s3demo.vhd
------------------------------------------------------------------------
-- S3demo.vhd -- Demonstrate basic Pegasus function
---------------------------------------------------------------------
www.eeworm.com/read/174989/9565754
vhd dregister.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity DRegister is
port( op: in std_logic;
clk: in std_logic;
din: in std_logic_vector(31 downto 0);
dout: out std_logic_vector(31 downt