arith_lib.vhd

Cadence的VHDL运算库包

-------------------------------------------------------------------------------
-- Title       : Library component declarations
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : arith_lib.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1997/11/04
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Package containing all component declarations.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library arith_lib;
use arith_lib.arith_utils.all;

package arith_lib is

  type speedType is (slow, medium, fast);

  -----------------------------------------------------------------------------
  -- Adders
  -----------------------------------------------------------------------------
  component Add
    generic (width : positive;
	     speed : speedType);
    port (A, B : in std_logic_vector(width-1 downto 0);
	  S : out std_logic_vector(width-1 downto 0));
  end component;

  component AddC
    generic (width : positive;
	     speed : speedType);
    port (A, B : in std_logic_vector(width-1 downto 0);
	  CI : in std_logic;
	  S : out std_logic_vector(width-1 downto 0);
	  CO : out std_logic);
  end component;

  component AddV
    generic (width : positive;
	     speed : speedType);
    port (A, B : in std_logic_vector(width-1 downto 0);
	  CI : in std_logic;
	  S : out std_logic_vector(width-1 downto 0);
	  V : out std_logic);
  end component;

  component AddCfast
    generic (width : positive;
	     speed : speedType);
    port (A, B : in std_logic_vector(width-1 downto 0);
	  CI : in std_logic;
	  S : out std_logic_vector(width-1 downto 0);
	  CO : out std_logic);
  end component;

  component AddCendaround
    generic (width : positive;
	     speed : speedType);
    port (A, B : in std_logic_vector(width-1 downto 0);
          CI : in std_logic;
          S : out std_logic_vector(width-1 downto 0);
          CO : out std_logic);
  end component;

  component AddMod2Nm1
    generic (width : positive;
	     speed : speedType);
    port (A, B : in std_logic_vector(width-1 downto 0);
	  S : out std_logic_vector(width-1 downto 0));
  end component;

  component AddMod2Nm1s0
    generic (width : positive;
	     speed : speedType);
    port (A, B : in std_logic_vector(width-1 downto 0);
	  S : out std_logic_vector(width-1 downto 0));
  end component;

  component AddMod2Np1
    generic (width : positive;
	     speed : speedType);
    port (A, B : in std_logic_vector(width-1 downto 0);
	  S : out std_logic_vector(width-1 downto 0));
  end component;

  component AddCsv
    generic (width : positive);
    port (A1, A2, A3 : in std_logic_vector(width-1 downto 0);
	  S, C : out std_logic_vector(width-1 downto 0));
  end component;

  component AddMopCsv
    generic (width : positive;
	     depth : positive;
	     speed : speedType);
    port (A : in std_logic_vector(depth*width-1 downto 0);
	  S, C : out std_logic_vector(width-1 downto 0));
  end component;

  component AddMop
    generic (width : positive;
	     depth : positive;
	     speed : speedType);
    port (A : in std_logic_vector(depth*width-1 downto 0);
	  S : out std_logic_vector(width-1 downto 0));
  end component;

  -----------------------------------------------------------------------------
  -- Subtractors
  -----------------------------------------------------------------------------
  component Sub
    generic (width : positive;
	     speed : speedType);
    port (A, B : in std_logic_vector(width-1 downto 0);
	  S : out std_logic_vector(width-1 downto 0));
  end component;

  component SubC
    generic (width : positive;
	     speed : speedType);
    port (A, B : in std_logic_vector(width-1 downto 0);
	  CI : in std_logic;
	  S : out std_logic_vector(width-1 downto 0);
	  CO : out std_logic);
  end component;

  component SubCZ
    generic (width : positive;
	     speed : speedType);
    port (A, B : in std_logic_vector(width-1 downto 0);
	  CI : in std_logic;
	  S : out std_logic_vector(width-1 downto 0);
	  CO, Z : out std_logic);
  end component;

  component SubV
    generic (width : positive;
	     speed : speedType);
    port (A, B : in std_logic_vector(width-1 downto 0);
	  CI : in std_logic;
	  S : out std_logic_vector(width-1 downto 0);
	  V : out std_logic);
  end component;

  component SubVZ
    generic (width : positive;
	     speed : speedType);
    port (A, B : in std_logic_vector(width-1 downto 0);
	  CI : in std_logic;
	  S : out std_logic_vector(width-1 downto 0);
	  V, Z : out std_logic);
  end component;

  -----------------------------------------------------------------------------
  -- Adder/Subtractors
  -----------------------------------------------------------------------------
  component AddSub
    generic (width : positive;
	     speed : speedType);
    port (A, B : in std_logic_vector(width-1 downto 0);
          SUB : in std_logic;
	  S : out std_logic_vector(width-1 downto 0));
  end component;

  component AddSubC
    generic (width : positive;
	     speed : speedType);
    port (A, B : in std_logic_vector(width-1 downto 0);
	  CI : in std_logic;
          SUB : in std_logic;
	  S : out std_logic_vector(width-1 downto 0);
	  CO : out std_logic);
  end component;

  component AddSubV
    generic (width : positive;
	     speed : speedType);
    port (A, B : in std_logic_vector(width-1 downto 0);
	  CI : in std_logic;
          SUB : in std_logic;
	  S : out std_logic_vector(width-1 downto 0);
	  V : out std_logic);
  end component;

  -----------------------------------------------------------------------------
  -- Incrementers and Decrementers
  -----------------------------------------------------------------------------
  component Inc
    generic (width : positive;
	     speed : speedType);
    port (A : in std_logic_vector(width-1 downto 0);
	  Z : out std_logic_vector(width-1 downto 0));
  end component;

  component IncGray
    generic (width : positive;
	     speed : speedType);
    port (A : in std_logic_vector(width-1 downto 0);
	  Z : out std_logic_vector(width-1 downto 0));
  end component;

  component IncC
    generic (width : positive;
	     speed : speedType);
    port (A : in std_logic_vector(width-1 downto 0);
	  CI : in std_logic;
	  Z : out std_logic_vector(width-1 downto 0);
	  CO : out std_logic);
  end component;

  component IncGrayC
    generic (width : positive;
	     speed : speedType);
    port (A : in std_logic_vector(width-1 downto 0);
	  CI : in std_logic;
	  Z : out std_logic_vector(width-1 downto 0));
  end component;

  component Dec
    generic (width : positive;
	     speed : speedType);
    port (A : in std_logic_vector(width-1 downto 0);
	  Z : out std_logic_vector(width-1 downto 0));
  end component;

  component DecC
    generic (width : positive;
	     speed : speedType);
    port (A : in std_logic_vector(width-1 downto 0);
	  CI : in std_logic;
	  Z : out std_logic_vector(width-1 downto 0);
	  CO : out std_logic);
  end component;

  component IncDec
    generic (width : positive;
	     speed : speedType);
    port (A : in std_logic_vector(width-1 downto 0);
          DEC : in std_logic;
	  Z : out std_logic_vector(width-1 downto 0));
  end component;

  component IncDecC
    generic (width : positive;
	     speed : speedType);
    port (A : in std_logic_vector(width-1 downto 0);
	  CI : in std_logic;
          DEC : in std_logic;
	  Z : out std_logic_vector(width-1 downto 0);
	  CO : out std_logic);
  end component;

  component Neg
    generic (width : positive;
	     speed : speedType);
    port (A : in std_logic_vector(width-1 downto 0);
	  Z : out std_logic_vector(width-1 downto 0));
  end component;

  component NegC
    generic (width : positive;
	     speed : speedType);
    port (A : in std_logic_vector(width-1 downto 0);
	  Neg : in std_logic;
	  Z : out std_logic_vector(width-1 downto 0));
  end component;

  component AbsVal
    generic (width : positive;
	     speed : speedType);
    port (A : in std_logic_vector(width-1 downto 0);
	  Z : out std_logic_vector(width-1 downto 0));
  end component;

  -----------------------------------------------------------------------------
  -- Multipliers
  -----------------------------------------------------------------------------
  component MulUns
    generic (widthX : positive;
	     widthY : positive;
	     speed : speedType);
    port (X : in std_logic_vector(widthX-1 downto 0);
	  Y : in std_logic_vector(widthY-1 downto 0);
	  P : out std_logic_vector(widthX+widthY-1 downto 0));
  end component;

  component MulSgn
    generic (widthX : positive;
	     widthY : positive;
	     speed : speedType);
    port (X : in std_logic_vector(widthX-1 downto 0);
	  Y : in std_logic_vector(widthY-1 downto 0);
	  P : out std_logic_vector(widthX+widthY-1 downto 0));
  end component;

  component MulAddUns
    generic (widthX : positive;
	     widthY : positive;
	     widthA : positive;
	     speed : speedType);
    port (X : in std_logic_vector(widthX-1 downto 0);
	  Y : in std_logic_vector(widthY-1 downto 0);
	  A : in std_logic_vector(widthA-1 downto 0);
	  P : out std_logic_vector(widthA-1 downto 0));
  end component;

  component MulAddSgn
    generic (widthX : positive;
	     widthY : positive;
	     widthA : positive;
	     speed : speedType);
    port (X : in std_logic_vector(widthX-1 downto 0);
	  Y : in std_logic_vector(widthY-1 downto 0);
	  A : in std_logic_vector(widthA-1 downto 0);
	  P : out std_logic_vector(widthA-1 downto 0));
  end component;

  component AddMulUns
    generic (widthX : positive;
	     widthY : positive;
	     speed : speedType);
    port (XS, XC : in std_logic_vector(widthX-1 downto 0);
	  Y : in std_logic_vector(widthY-1 downto 0);
	  P : out std_logic_vector(widthX+widthY-1 downto 0));
  end component;