fourbitincrement.vhd.bak

用VHDL编译的源代码

library ieee;
use ieee.std_logic_1164.all;
entity fourbitincrement is
port(
       a:in std_logic_vector(3 downto 0);
       y:out std_logic_vector(6 downto 0)
);
end fourbitincrement;

architecture one of fourbitincrement is
COMPONENT onebitincrement 
port(
      i,cin: in std_logic;
      cout,s: out std_logic
   );
end COMPONENT;

COMPONENT xnor2
port(
      a,b: in std_logic;
      c: out std_logic
   );
end COMPONENT;

signal d,e,f,g: std_logic;
begin
u5: xnor2 port map(a=>a(0), b=>a(0), c=>d);
u1: onebitincrement port map(cin=>d, i=>a(0), s=>y(0), cout=>e);
u2: onebitincrement port map(cin=>e, i=>a(1), s=>y(1), cout=>f);
u3: onebitincrement port map(cin=>f, i=>a(2), s=>y(2), cout=>g);      
u4: onebitincrement port map(cin=>g, i=>a(3), s=>y(3)         );
end one;