reg_exchange.vhd

提供了一个硬判决的viterbi译码器（2

--reg_exchange.vhd
--v0.1
--output measure

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity reg_exchange is
	port(
		clk: in std_logic;
 		reset: in std_logic;
		acs_0: in std_logic;
		acs_1: in std_logic;
		acs_2: in std_logic;
		acs_3: in std_logic;
		ireg0: in std_logic_vector(9 downto 0);
		ireg1: in std_logic_vector(9 downto 0);
		ireg2: in std_logic_vector(9 downto 0);
		ireg3: in std_logic_vector(9 downto 0);	
		oreg0: out std_logic_vector(9 downto 0);
		oreg1: out std_logic_vector(9 downto 0);
		oreg2: out std_logic_vector(9 downto 0);
		oreg3: out std_logic_vector(9 downto 0);
	    sout0: out std_logic;
		sout1: out std_logic;	
		sout2: out std_logic;
		sout3: out std_logic
		);
end reg_exchange;

architecture a of reg_exchange is
signal w0: std_logic_vector(9 downto 0);
signal w1: std_logic_vector(9 downto 0);
signal w2: std_logic_vector(9 downto 0);
signal w3: std_logic_vector(9 downto 0);
begin
	process(clk,ireg0,ireg1,ireg2,ireg3,acs_0,acs_1,acs_2,acs_3)
	begin
	if rising_edge(clk) then
	 	if reset='1' then
            w0<=(others=>'0');
            w1<=(others=>'0');
            w2<=(others=>'0');
            w3<=(others=>'0');
		else
			if acs_0='0' then
				w0<=ireg0(8 downto 0) & '0';
			else
				w0<=ireg2(8 downto 0) & '0';	
	    	end if;
	
			if acs_1='0' then
				w1<=ireg0(8 downto 0) & '1';
			else
				w1<=ireg2(8 downto 0) & '1';	
	   		end if;
	
			if acs_2='0' then
				w2<=ireg1(8 downto 0) & '0';
			else
				w2<=ireg3(8 downto 0) & '0';	
	    	end if;
	
			if acs_3='0' then
				w3<=ireg1(8 downto 0) & '1';
			else
				w3<=ireg3(8 downto 0) & '1';	
	    	end if;
		end if;
	end if;
	end process;
	oreg0<=w0;
	oreg1<=w1;
	oreg2<=w2;
	oreg3<=w3;
	sout0<=w0(9);
	sout1<=w1(9);
	sout2<=w2(9);
	sout3<=w3(9);
end a;