dregister.vhd

来自「the booth algorithm to implement the 32b」· VHDL 代码 · 共 25 行

library IEEE;
use IEEE.std_logic_1164.all;

entity DRegister is 
port( op: in std_logic;
      clk: in std_logic;
      din: in std_logic_vector(31 downto 0);
      dout: out std_logic_vector(31 downto 0)
      );
end DRegister;

architecture behav of DRegister is
signal data: std_logic_vector(31 downto 0);
begin
reg: process(clk)
begin
    if (clk'event and clk = '1') then
        if (op = '1') then
            data <= din;
        end if;
        
        dout <= data;
    end if;
end process;
end behav;