代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/382450/9026225
vhd mux8.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity mux8 is
port(
a,b,c,d,e,f:in std_logic_vector(3 downto 0);
clk:in std_logi
www.eeworm.com/read/382447/9029087
vhd seven.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY seven IS
PORT
( men: IN std_logic_vector(6 downto 0);
pass: buffer std_logic
);
END seven;
ARCHITECTURE beha
www.eeworm.com/read/382353/9033718
bak temp.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity temp is
port(
p : out std_logic;
reset: in std_logic;
www.eeworm.com/read/382353/9033914
vhd temp.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity temp is
port(
p : out std_logic;
reset: in std_logic;
www.eeworm.com/read/382345/9034492
txt saomiao.txt
library ieee;
use ieee.std_logic_1164.all;
entity saomiao is
port(clk:in std_logic;
d3,d2,d1,d0:in std_logic_vector(3 downto 0);
q:out std_logic_vector(3 downto 0);
www.eeworm.com/read/185487/9035016
vhd stime.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
www.eeworm.com/read/185356/9041986
vhd leijiaqi.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity leijiaqi is
port(clk:in std_logic;
y:out std_logic);
end;
architecture main of leijiaqi is
signal
www.eeworm.com/read/382145/9045694
vhd colour.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity colour is
port (
key1:in std_logic;
color:buffer integer range
www.eeworm.com/read/382145/9045804
vhd colour.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity colour is
port (
key1:in std_logic;
color:buffer integer range
www.eeworm.com/read/382145/9045844
bak colour.vhd.bak
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity colour is
port (
key1:in std_logic;
color:buffer integer