📄 temp.vhd.bak
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity temp is
port(
p : out std_logic;
reset: in std_logic;
inclk : in std_logic;
inkey : in std_logic_vector(3 downto 0);
outkey : out std_logic_vector(3 downto 0);
outled : out std_logic_vector(6 downto 0));
end temp;
architecture art of temp is
component yanshi --例化延时去抖动模块
port(
reset : in std_logic;
clk,a : in std_logic;
b : out std_logic);
end component;
signal keyclk : std_logic_vector(17 downto 0);
signal chuclk : std_logic_vector(3 downto 0);
signal keyclkout ,chuclkout : std_logic;
signal chuout : std_logic_vector(3 downto 0);
signal inkeymap : std_logic_vector(3 downto 0);
signal keyout : std_logic_vector(7 downto 0);
signal bb : std_logic_vector(1 downto 0);
begin
roll: for i in 0 to 3 generate
movskipx : yanshi port map(reset,inkey(i),keyclkout,inkeymap(i));
end generate;
clk_key: process(inclk) --例化用到的时钟信号50MS
begin
if(inclk ' event and inclk = '1') then
if(keyclk=250000) then
keyclk<="000000000000000000";
keyclkout<= not keyclkout;
else
keyclk<=keyclk+1;
end if;
end if;
end process clk_key;
clk_chu: process(keyclkout) -- 10分频后送到列扫描时钟5ms
begin
if(keyclkout 'event and keyclkout='1') then
if(chuclk = 9) then
chuclk<="0000";
chuclkout <= not chuclkout ;
else
chuclk<=chuclk+1;
end if;
end if;
end process clk_chu;
clk_chu_out: process(reset,chuclkout)
begin
if(reset='0') then
bb<="00";
elsif(chuclkout 'event and chuclkout = '1')then
if(bb="11")then
bb<="00";
else bb<=bb+1;
end if;
case bb is
when "00"=>chuout<="1110";
when "01"=>chuout<="1101";
when "10"=>chuout<="1011";
when "11"=>chuout<="0111";
when others=>null;
end case;
end if;
end process clk_chu_out;
out_led: process(keyout,reset,chuclkout)
begin
p<='0';
if(reset='0') then
outled<="0000000";
elsif chuclkout 'event and chuclkout = '1' then
case keyout(3 downto 0) is
when "0111"=>case keyout(7 downto 4) is
when "0111"=>outled<="1111001"; --1
when "1011"=>outled<="0011001"; --2
when "1101"=>outled<="1111000"; --3
when "1110"=>outled<="0100011"; --u
when others=>null;
end case;
when "1011"=>case keyout(7 downto 4) is
when "0111"=>outled<="0100100"; --4
when "1011"=>outled<="0010010"; --5
when "1101"=>outled<="0000000"; --6
when "1110"=>outled<="1000000"; --d
when others=>null;
end case;
when "1101"=>case keyout(7 downto 4) is
when "0111"=>outled<="0110000"; --7
when "1011"=>outled<="0000010"; --8
when "1101"=>outled<="0010000"; --9
when "1110"=>outled<="0000110"; --e
when others=>null;
end case;
when "1110"=>case keyout(7 downto 4) is
when "0111"=>outled<="1000001"; --o*
when "1011"=>outled<="0100001"; --0
when "1101"=>outled<="0111111";
when "1110"=>outled<="1000110";
when others=>null;
end case;
when others=>null;
end case;
end if;
end process out_led;
outkey<=chuout;
keyout<=chuout&inkey;
end art;
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