stime.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity stime is
    Port ( clk : in std_logic;
		   hlclk : in std_logic_vector(0 to 1);
		  lsclk : in std_logic_vector(0 to 1);
           tout : out std_logic;
		  mout:out std_logic);
end stime;

architecture Behavioral of stime is

signal temp:std_logic_vector(24 downto 0);

begin

process(clk,hlclk)
begin
     if clk'event and clk='1' then
		temp<=temp+1 ;
    end if;
       case hlclk is
	  when "00"=> mout<=temp(4);
	  when "01"=> mout<=temp(3);
	  when "10"=> mout<=temp(2);
	  when "11"=> mout<=temp(1);
	  when others => null;
	  end case;
	  case  lsclk is
	  when "00"=> tout<=clk;
	  when "01"=> tout<=temp(2);
	  when "10"=> tout<=temp(1);
	  when "11"=> tout<=temp(0);
	  when others => null;
	  end case;
	  -- tout<=temp(1);
	 --  mout<=temp(2);
end process;

end Behavioral;