📄 saomiao.txt
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library ieee;
use ieee.std_logic_1164.all;
entity saomiao is
port(clk:in std_logic;
d3,d2,d1,d0:in std_logic_vector(3 downto 0);
q:out std_logic_vector(3 downto 0);
xuantong:out std_logic_vector(3 downto 0));
end;
architecture a of saomiao is
type st is(st0,st1,st2,st3);
signal m:st;
begin
process(clk)
begin
if clk'event and clk='1' then
case m is
when st0=>q<=d3;xuantong<="0111";m<=st1;
when st1=>q<=d2;xuantong<="1011";m<=st2;
when st2=>q<=d1;xuantong<="1101";m<=st3;
when st3=>q<=d0;xuantong<="1110";m<=st0;
when others=>null;
end case;
end if;
end process;
end;
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