colour.vhd

来自「pwm控制模块 使用过很多次」· VHDL 代码 · 共 25 行

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity colour is
port ( 
       key1:in std_logic;
       color:buffer integer range 0 to 2  
      );
end colour;

architecture clr of colour is

begin
process(key1)
begin
if key1'event and key1='1' then
   if color=2 then
      color<=0;
   else color<=color+1;
   end if;
end if;
end process;
end clr;