代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/428593/8857040
vhd dpc.vhd
---------------------------------------------------------------------------
-- dpc (PWM generator)
---------------------------------------------------------------------------
library ieee;
use ieee.
www.eeworm.com/read/143894/8881835
vhd traffic.vhd
--
-- File: E:\traffic.vhd
-- created: 09/23/04 04:55:01
-- from: 'E:\traffic.asf'
-- by fsm2hdl - version: 2.0.1.60
--
library IEEE;
use IEEE.std_logic_1164.all;
-- SYNOPSYS library decl
www.eeworm.com/read/384170/8892622
vhd cnt60_2.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt60_2 is
port(clk:in std_logic;
s1,s0:out std_logic_vector(3 downto 0);
co:out std_logic);
end cnt60
www.eeworm.com/read/383774/8919942
vhd rdff.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rdff is
generic (size : integer := 2);
port (clk,reset : in std_logic;
d : in std_logic
www.eeworm.com/read/186459/8932652
vhdl litenandfsm.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
www.eeworm.com/read/427328/8951136
vhd reg32b.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG32B IS
PORT ( Load : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO
www.eeworm.com/read/427328/8951195
vhd reg10b.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG10B IS
PORT ( Load : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(9 DOWNTO
www.eeworm.com/read/284185/8956069
vhd 53_counter.vhd
library IEEE;
use IEEE.std_logic_1164.all;
package mycntpkg is
component count port(clk,rst : in std_logic;
cnt : inout std_logic_vector(2 downto 0));
end component;
end mycntpkg;
www.eeworm.com/read/383149/8968245
vhd mouse.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mouse is
Port (
clk : in std_logic;
reset : in std_logic;
ps2_clk : inout std_l
www.eeworm.com/read/283975/8973966
txt float_mul.txt
32位浮点乘法器vhdl源代码
library ieee;
use ieee.std_logic_1164.all;
entity full_adder is
port(x,y,z:in std_logic;s,c:out std_logic);
end full_adder;
architecture df of full_adder is
begin
s