代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/391071/8422312
vhd alaw_nl_l.vhd
library ieee;
use ieee.std_logic_1164.all;
entity alaw_nl_l is
port(
data :in std_logic; --pcm signal a
clock :in std_logic; --clock signal
framea :in std_logic
www.eeworm.com/read/390975/8430641
vhd uart.vhd
--/*******************************************************************
-- *
-- * DESCRIPTION: UART top level module implements full duplex UART function.
-- *
-- * AUTHOR: Jim Jian
-- *
-
www.eeworm.com/read/190964/8435911
vhd genxlib_arch.vhd
--------------------------------------------------------------------------------
-- Copyright(C) 2005 by Xilinx, Inc. All rights reserved.
-- This text/file contains proprietary, confidential
-- infor
www.eeworm.com/read/390877/8436094
vhd lifttt.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity lift is
port (
clkin:in STD_LOGIC;
upin:in STD_LOGIC;
downin:in STD_LOGIC;
st_ch:in STD_LOGIC;
www.eeworm.com/read/390877/8436112
bak lifttt.vhd.bak
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity lift is
port (
clkin:in STD_LOGIC;
upin:in STD_LOGIC;
downin:in STD_LOGIC;
st_ch:in STD_LOGIC;
www.eeworm.com/read/291128/8441309
vhd main.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity main is
port(clk1:in std_logic;
leda1,leda10a,ledb1,ledb10b:out std_logic_vect
www.eeworm.com/read/290889/8455600
vhd minute0.vhd
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY minute0 IS
PORT(
en : IN STD_LOGIC;
min1,min0 :out std_logic_vector(3 downto 0);
co
www.eeworm.com/read/290889/8455634
vhd ahour.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ahour is
port(en,mode :in std_logic;
h1,h0 :out std_logic_vector(3 downto 0));
end ahour;
archi
www.eeworm.com/read/390486/8462557
vhd clock.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity clock is
Port ( clk : in std_logic; --1Hz
reset :
www.eeworm.com/read/390483/8463156
vhd mul16.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity mul16 is
port(clk:in std_logic;
a:in std_logic_vector(15 downto 0);
b:i