alaw_nl_l.vhd

使用VHDL实现通信脉冲编码调制（PCM）中的a律转换

library ieee;
use ieee.std_logic_1164.all;

entity alaw_nl_l is
	port(
			data			:in			std_logic;						--pcm signal a
			clock			:in			std_logic;						--clock signal
			framea			:in			std_logic;						--frame synchronous signal
			frameb			:in			std_logic;						--frame synchronous signal
			ebi				:in			std_logic;						--enable odd bit(a-law) inversion.1:inverted;0:not inverted
			dataq			:out		std_logic_vector(12 downto 0));	--output overlap signal
end alaw_nl_l;

architecture structure of alaw_nl_l is
	COMPONENT s_p
		PORT(
			data			:in			std_logic;						--pcm signal a
			clock			:in			std_logic;						--clock signal
			frame			:in			std_logic;						--frame synchronous signal
			dataq			:out		std_logic_vector(7 downto 0));	--output overlap signal
	END COMPONENT;

	COMPONENT alaw_invert
		PORT(
			data			:in			std_logic_vector(7 downto 0);	--pcm signal a
			ebi				:in			std_logic;						--enable even bit(a-law) inversion.1:inverted;0:not inverted
			dataq			:out		std_logic_vector(7 downto 0));	--output overlap signal
	END COMPONENT;

	COMPONENT alaw_8_13
		PORT(
			data			:in			std_logic_vector(7 downto 0);	--pcm signal a
			frame			:in			std_logic;						--frame synchronous signal
			dataq			:out		std_logic_vector(12 downto 0));	--output overlap signal
	END COMPONENT;
	
	signal	data_s_p,data_invert	:std_logic_vector(7 downto 0);
begin
	u1:s_p
		port map(data	=> data,
				 clock	=> clock,
				 frame	=> framea,
				 dataq	=> data_s_p);
	u2:alaw_invert
		port map(data	=> data_s_p,
				 ebi	=> ebi,
				 dataq 	=> data_invert);
	u3:alaw_8_13
		port map(data	=> data_invert,
				 frame	=> frameb,
				 dataq 	=> dataq);
end structure;