mul16.vhd

基于CPLD/FPGA的十六位乘法器的VHDL实现

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity mul16 is
	port(clk:in std_logic;
		 a:in std_logic_vector(15 downto 0);
		 b:in std_logic_vector(15 downto 0);
		 q:out std_logic_vector(31 downto 0));
end mul16;

architecture behave of mul16 is
begin
	process(clk)
	variable temp:std_logic_vector(31 downto 0);
	variable tout:std_logic_vector(31 downto 0);
	begin
	tout:="00000000000000000000000000000000";
	if rising_edge(clk)then
		for i in 0 to 15 loop
			temp:="00000000000000000000000000000000";
				if(b(i)='1')then
					for j in 0 to 15 loop
						temp(i+j):=a(j);
					end loop;
				end if;
			tout:=temp+tout;
		end loop;
		q<=tout;
	end if;
	end process;
end behave;