mul16.map.summary

来自「基于CPLD/FPGA的十六位乘法器的VHDL实现」· SUMMARY 代码 · 共 13 行

Analysis & Synthesis Status : Successful - Fri Nov 14 20:31:27 2008
Quartus II Version : 8.0 Build 215 05/29/2008 SJ Full Version
Revision Name : mul16
Top-level Entity Name : mul16
Family : MAX II
Total logic elements : 524
Total pins : 65
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0